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OverviewAdopting new fabrication technologies not only provides higher integration and enhances performance, but also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz timing-related defects havv become a high proportion of the total chip defects. For nanometer technology designs, the stuck-at fault test alone cannot ensure a high quality level of chips. At-speed tests using the transition fault model has become a requirement in technologies below 180nm. Traditional at-speed test methods cannot guarantee high quality test results as they face many new challenges. Supply noise (including IR-drop, ground bounce, and Ldi/dt) effects on chip performance, high test pattern volume, low fault/defect coverage, small delay defect test pattern generation, high cost of test implementation and application, and utilizing low-cost testers are among these challenges. This book discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the transition fault test. Full Product DetailsAuthor: Nisar Ahmed , Nisar AhmedPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: 2008 Dimensions: Width: 15.50cm , Height: 1.50cm , Length: 23.50cm Weight: 0.462kg ISBN: 9781441945594ISBN 10: 1441945598 Pages: 281 Publication Date: 14 December 2011 Audience: Professional and scholarly , College/higher education , Professional & Vocational , Postgraduate, Research & Scholarly Format: Paperback Publisher's Status: Active Availability: Out of stock  The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available. Table of ContentsIntroduction to path delay and transition delay fault models and test methods.- At-speed test challenges for nanometer technology designs.- Low-cost tester friendly design-for-test techniques.- Improving test quality of current at-speed test methods.- Functionally untestable fault list generation and avoidance.- Timing-based ATPG for screening small delay faults.- Faster-than-at-speed test considering IR-drop effects.- IR-drop tolerant at-speed test pattern generation and application.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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