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OverviewMulti-chips modules (MCMs) in the late 1990s consist of complex and dense VLSI devices mounted into packages that allow little physical access to internal nodes. The complexity and cost associated with their test and diagnosis are major obstacles to their use. This volume of research presents updated test strategies for MCMs. It is designed for engineers interested in practical implementations of MCM test solutions and for designers seeking current test and design-for-testability solutions for their next designs. Full Product DetailsAuthor: Yervant Zorian , V.D. AgrawalPublisher: Springer Imprint: Springer Edition: Reprinted from JOURNAL OF ELECTRONIC TESTING, 10:1-2, 1997 Volume: 7 Dimensions: Width: 20.30cm , Height: 1.10cm , Length: 25.40cm Weight: 0.576kg ISBN: 9780792399209ISBN 10: 079239920 Pages: 167 Publication Date: 31 May 1997 Audience: Professional and scholarly , General/trade , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: Out of stock  The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available. Table of ContentsFundamentals of MCM Testing and Design-for-Testability.- Die Level Testing.- Known Good Die.- Substrate Testing.- A Survey of Test Techniques for MCM Substrates.- Smart Substrate MCMs.- Electron Beam Probing—A Solution for MCM Test and Failure Analysis.- Module Level Test.- MCM Test Strategy Synthesis from Chip Test and Board Test Approaches.- Designing “Dual Personality” IEEE 1149.1 Compliant Multi-Chip Modules.- An Effective Multi-Chip BIST Scheme.- MCM Test Applications.- Design-for-Test in a Multiple Substrate Multichip Module.- A Test Methodology for High Performance MCMs.- Module Level Diagnosis.- A Formalization of the IEEE 1149.1-1990 Diagnostic Methodology as Applied to Multichip Modules.- Multichip Module Diagnosis by Product-Code Signatures.- Simulation Techniques for MCMs.- Simulation Techniques for the Manufacturing Test of MCMs.- MCM Test Economics.- Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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