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OverviewThis text covers a wide range of model applications and research. It begins by describing a model generator to create component models and goes on to discuss ASIC design and ASIC library generation. This section includes chapters on the requirements for developing an ASIC library, a case study in which VITAL is used to create such a library, and the analysis and description of the accuracy required in modelling interconnections in ASIC design. Other chapters describe the development of thermal models for electronic devices, the development of a set of model packages for VHDL floating point operations, a technique for model validation and verification and a tool for model encryption. The book aims to provide an essential update for users, vendors, model producers, technical managers, designers and researchers working in electronic design. Full Product DetailsAuthor: Jean-Michel Bergé , Oz Levia , Jacques RouillardPublisher: Springer Imprint: Springer Edition: 1995 ed. Volume: 1 Dimensions: Width: 15.50cm , Height: 1.10cm , Length: 23.50cm Weight: 0.940kg ISBN: 9780792395683ISBN 10: 0792395689 Pages: 155 Publication Date: 30 April 1995 Audience: Professional and scholarly , General/trade , College/higher education , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of Contents1. A Flexible Generator of Component Models.- 1.1. Introduction.- 1.2. G&D Generator.- 1.3. A Flexible Generator.- 1.4. Implementation of the Generator.- 1.5. Experimental Results.- 1.6. Conclusions and Future Work.- 2. What Makes an Asic Library Sign-Off.- 2.1. Introduction.- 2.2. Testing.- 2.3. Accuracy.- 2.4. Library Creation.- 2.5. Conclusion.- 3. A Case History in Building Vital-Compliant Models.- 3.1. Introduction: from VHDL to VITAL.- 3.2. Evolution of VITAL Specification.- 3.3. Simulation Performances.- 3.4. Conclusion and Future Work.- 4. Modeling Multiple Driver Net Delay in Simulation.- 4.1. Wire Delay.- 4.2. Wire Delay Modeling Alternatives.- 4.3. Modeling Wire Delay.- 4.4. Wire Delay Model Integration.- 4.5. Summary.- 5. Delphi: The Development of Libraries of Physical Models of Electronic Components for an Integrated Design Environment.- 5.1. Background.- 5.2. The DELPHI Project.- 5.3. Preliminary Investigations of compact models for Mono-Chip Packages.- 5.4. A Compact Model of a 208-Lead PQFP Package.- 5.5. Concluding Remarks.- 6. VHDL Floating Point Operations.- 6.1. Introduction.- 6.2. Framework for VHDL Code.- 6.3. Operations.- 6.4. Validation and Benchmarking.- 6.5. Package Usability.- 6.6. Conclusions.- 7. Symbolic Model Checking with Past and Future Temporal Modalities: Fundamentals and Algorithms.- 7.1. Introduction.- 7.2. Fundamentals.- 7.3. The Temporal Logic.- 7.4. Algorithms of the Symbolic Model Checker.- 7.5. Application to VHDL.- 7.6. Conclusion.- 8. Krypton: Portable, Non-Reversible Encryption for VHDL.- 8.1. Introduction.- 8.2. VHDL Source-Source Encryption.- 8.3. LVS: A Compilation Environment for VHDL-Based Applications.- 8.4. Running KRYPTON.- 8.5. Example.- 8.6. Conclusions and Perspectives.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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