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OverviewA complete reference manual to the MIPS RISC architecture.* describes the user Instruction Set Architecture (ISA), as implemented by the R2000, R3000, R4000, and R6000 (collectively known as the R-Series) processors, together with an extension to this ISA. * describes the general characteristics and capabilities of each RISC processor, along with a description of the programming model, memory management unit (MMU), and the registers associated with each processor. * includes an overview of the underlying concepts that distinguish RISC architecture from Complex Instruction Set Computer (CISC) architecture. Full Product DetailsAuthor: Gerry Kane , Joseph Heinrich , Joseph HeinrichPublisher: Pearson Education (US) Imprint: Prentice Hall Edition: 2nd edition Dimensions: Width: 23.40cm , Height: 2.20cm , Length: 17.80cm Weight: 0.839kg ISBN: 9780135904725ISBN 10: 0135904722 Pages: 544 Publication Date: 01 February 1992 Audience: College/higher education , Tertiary & Higher Education Format: Paperback Publisher's Status: Out of Print Availability: Out of stock  Table of Contents1. RISC Architecture: An Overview. 2. MIPS Processor Architecture Overview. 3. CPU Instruction Set Summary. 4. Memory Management System. 5. Caches. 6. Exception Processing. 7. FPU Overview. 8. FPU Instruction Set Summary and Instruction Pipeline. 9. Floating Point Exceptions. Appendixes. Index.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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