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OverviewThis paper surveys key research challenges and recent results of manufacturability aware routing in nanometer VLSI designs. The manufacturing challenges have their root causes from various integrated circuit (IC) manufacturing processes and steps, e.g., deep sub-wavelength lithography, random defects, via voids, chemical-mechanical polishing, and antenna-effects. They may result in both functional and parametric yield losses. The manufacturability aware routing can be performed at different routing stages including global routing, track routing, and detail routing, guided by both manufacturing process models and manufacturing-friendly rules. The manufacturability/yield optimization can be performed through both correct-by-construction (i.e., optimization during routing) as well as construct-by-correction (i.e., post-routing optimization). This paper provides a holistic view of key design for manufacturability issues in nanometer VLSI routing. Full Product DetailsAuthor: David Z. Pan , Minsik Cho , Kun Yuan , Kun YuanPublisher: now publishers Inc Imprint: now publishers Inc Volume: 11 Dimensions: Width: 15.60cm , Height: 0.60cm , Length: 23.40cm Weight: 0.170kg ISBN: 9781601983503ISBN 10: 1601983506 Pages: 112 Publication Date: 04 May 2010 Audience: General/trade , General Format: Paperback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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