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OverviewThis book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses. Full Product DetailsAuthor: Sandeep SainiPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: 2012 Volume: 117 Dimensions: Width: 15.50cm , Height: 1.10cm , Length: 23.50cm Weight: 0.482kg ISBN: 9781461413226ISBN 10: 1461413222 Pages: 152 Publication Date: 15 June 2015 Audience: College/higher education , Postgraduate, Research & Scholarly Format: Hardback Publisher's Status: Active Availability: Manufactured on demand  We will order this item for you from a manufactured on demand supplier. Table of ContentsPart I Basics of Interconnect Design.- Introduction to Interconnects.- CMOS Buffer.- Part II Buffer and Schmidt trigger Insertion Techniques for Low Power Interconnect Design.- Buffer Insertion as a Solution to Interconnect Issues.- Schmidt Trigger Approach.- Part III Bus Coding Techniques for Low Power Interconnect Design.- Bus Coding Techniques.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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