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OverviewLogic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints. Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis. Full Product DetailsAuthor: Sasan Iman , Massoud PedramPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: Softcover reprint of the original 1st ed. 1998 Dimensions: Width: 15.50cm , Height: 1.30cm , Length: 23.50cm Weight: 0.397kg ISBN: 9781461374909ISBN 10: 1461374901 Pages: 236 Publication Date: 24 October 2012 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Manufactured on demand  We will order this item for you from a manufactured on demand supplier. Table of ContentsI Background, Terminology, and Power Modeling.- 1 Introduction.- 2 Technology Independent Power Analysis and Modeling.- II Two-level Function Optimization for Low Power.- 3 Two-Level Logic Minimization in CMOS Circuits.- 4 Two-Level Logic Minimization in PLAs.- III Multi-level Network Optimization for Low Power.- 5 Logic Restructuring for Low Power.- 6 Logic Minimization for Low Power.- 7 Technology Dependent Optimization for Low Power.- 8 Post Mapping Structural Optimization for Low Power.- IV Power Optimization Methodology.- 9 POSE: Power Optimization and Synthesis Environment.- V Conclusion.- 10 Concluding Remarks.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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