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OverviewThis book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations). This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation. This book is an interesting and valuable resource for students and postgraduates in the area of computer science, as well as for designers of digital systems that included complex control units Full Product DetailsAuthor: Alexander Barkalov , Larysa Titarenko , Jacek BieganowskiPublisher: Springer International Publishing AG Imprint: Springer International Publishing AG Edition: Softcover reprint of the original 1st ed. 2018 Volume: 113 Weight: 3.635kg ISBN: 9783319867144ISBN 10: 3319867148 Pages: 225 Publication Date: 12 May 2018 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Manufactured on demand  We will order this item for you from a manufactured on demand supplier. Table of ContentsIntroduction.- Finite state machines and field-programmable gate arrays.- Linear chains in FSMs.- Hardware reduction for Moore UFSMs.- Hardware reduction for Mealy UFSMs.- Hardware reduction for Moore NFSMs.- Hardware reduction for Moore XFSMs.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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