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OverviewShort turnaround has become critical in the design of electronic systems. Software-programmable components such as microprocessors and digital signal processors have been used extensively in such systems since they allow rapid design revisions. However, the inherent performance limitations of software-programmable systems mean that they are inadequate for high-performance designs. Designers thus turned to gate arrays as a solution. User-programmable gate arrays (field-programmable gate arrays, FPGAs) have recently emerged and are changing the way electronic systems are designed and implemented. The growing complexity of the logic circuits that can be packed onto an FPGA chip means that it has become important to have automatic synthesis tools that implement logic functions on these architectures. This text describes logic synthesis for both look-up table (LUT) and multiplexor-based architectures, with a balanced presentation of existing techniques together with algorithms and the system developed by the authors. It should be a useful reference for VLSI designers, developers of computer-aided design tools, and anyone involved in or with FPGAs. Full Product DetailsAuthor: Rajeev Murgai , Robert K. Brayton , Alberto L. Sangiovanni-VincentelliPublisher: Springer Imprint: Springer Edition: 1995 ed. Volume: 324 Dimensions: Width: 15.50cm , Height: 2.50cm , Length: 23.50cm Weight: 1.780kg ISBN: 9780792395966ISBN 10: 0792395964 Pages: 427 Publication Date: 31 July 1995 Audience: College/higher education , Professional and scholarly , General/trade , Postgraduate, Research & Scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsI Introduction.- 1 Introduction.- 2 Background.- II Look-up Table (LUT) Architectures.- 3 Mapping Combinational Logic.- 4 Logic Optimization.- 5 Complexity Issues.- 6 Mapping Sequential Logic.- 7 Performance Directed Synthesis.- III Multiplexor-Based Architectures.- 8 Mapping Combinational Logic.- IV Conclusions.- 9 Conclusions.- References.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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