Overview

Research and development of logic synthesis and verification have matured considerably over the last two decades of the 20th century. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges. This text provides a state-of-the-art view of logic synthesis and verification. It consists of 15 chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references. The book chapters are written by 28 recognized leaders in the field and reviewed by equally qualified experts; the topics collectively span the field. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field.

Full Product Details

Author:   Soha Hassoun ,  Tsutomu Sasao
Publisher:   Springer
Imprint:   Springer
Edition:   2002 ed.
Volume:   654
Dimensions:   Width: 15.50cm , Height: 2.50cm , Length: 23.50cm
Weight:   1.840kg
ISBN:  

9780792376064

ISBN 10:   0792376064
Pages:   454
Publication Date:   30 November 2001
Audience:   College/higher education ,  Professional and scholarly ,  Undergraduate ,  Postgraduate, Research & Scholarly
Format:   Hardback
Publisher's Status:   Active
Availability:   Awaiting stock  
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Table of Contents

1 Two-Level Logic Minimization.- 1.1 Introduction.- 1.2 Exact Logic Minimization.- 1.3 Heuristic Logic Minimization.- 1.4 Conclusion.- 2 Multi-Level Logic Optimization.- 2.1 Introduction.- 2.2 Algebraic Methods.- 2.3 Boolean Methods.- 2.4 Functional Decomposition.- 2.5 Conclusions and Perspectives.- 2.6 Acknowledgments.- 3 Flexibility in Logic.- 3.1 Introduction.- 3.2 Environment.- 3.3 Types of Flexibility.- 3.4 Historical Perspective.- 4 Multiple-Valued Logic Synthesis and Optimization.- 4.1 Introduction.- 4.2 Multiple-Valued Functions.- 4.3 Functional Completeness.- 4.4 Chain-Based Post Algebra.- 4.5 Representations of Multiple-Valued Functions.- 4.6 Two-level Logic Optimization.- 4.7 Multi-Level Logic Optimization.- 4.8 Summary.- 4.9 Historical Perspectives.- 5 Technology Mapping.- 5.1 Introduction.- 5.2 Decomposition.- 5.3 Pattern Matching.- 5.4 Covering.- 5.5 Other Costs.- 5.6 Conclusions and Perspectives.- 6 Technology-based Transformations.- 6.1 Introduction.- 6.2 Gate Delay Models.- 6.3 Logic Transformations.- 6.4 Trends.- 7 Logical and Physical Design: A flow Perspective.- 7.1 Introduction.- 7.2 Logical and Physical Design Challenges.- 7.3 Survey of Current Design Flows.- 7.4 Refinement-based Flow.- 7.5 Conclusion & Perspective.- 8 Logic Synthesis for Low Power.- 8.1 Introduction.- 8.2 Gate-Level Techniques.- 8.3 Register-Transfer Level Techniques.- 8.4 The Evolution of Low-Power Synthesis.- 8.5 Conclusions.- 9 Optimization of Synchronous Circuits.- 9.1 Introduction.- 9.2 State-Based Techniques.- 9.3 Structural Techniques.- 9.4 Future Challenges.- 10 Asynchronous Control Circuits.- 10.1 Introduction.- 10.2 Burst-Mode Circuits.- 10.3 Speed-Independent Circuits.- 10.4 Conclusions.- 11 Ordered Binary Decision Diagrams.- 11.1 Introduction.- 11.2 Data Structures forSwitching Functions.- 11.3 OBDDs — Ordered Binary Decision Diagrams.- 11.4 Paradigmatic Applications of OBDDs.- 11.5 Optimization of Variable Ordering.- 11.6 Various Improvements of the BDD Data Structure.- 11.7 WWW-Portal for BDD Research.- 12 SAT and ATPG: Algorithms for Boolean Decision Problems.- 12.1 Introduction.- 12.2 SAT and ATPG Problem Formulations.- 12.3 Combinational Deterministic ATPG.- 12.4 SAT Algorithms: A Taxonomy.- 12.5 Search Acceleration Techniques.- 12.6 Implementation Issues.- 12.7 Historical Perspectives and Open Problems.- 13 Combinational and Sequential Equivalence Checking.- 13.1 Introduction.- 13.2 Problem Definition.- 13.3 General Approach to Formal Equivalence Checking.- 13.4 Deriving the Invariant ?.- 13.5 Combinational Equivalence Checking.- 13.6 Sequential Equivalence Checking.- 13.7 Implementation and Application Issues.- 13.8 Summary and Future Problems.- 14 Static Timing Analysis.- 14.1 Introduction.- 14.2 Basics.- 14.3 Path Exceptions.- 14.4 Transparent Latches.- 14.5 Incremental Timing Analysis.- 14.6 Statistical Timing Analysis.- 14.7 Summary and Future Challenges.- 14.8 Historical Perspective.- 15 The Future of Logic Synthesis and Verification.- 15.1 Logic Synthesis – Introduction.- 15.2 Techniques On The Edge.- 15.3 Physical/Logical Design.- 15.4 DSM Issues.- 15.5 Design For Low Power.- 15.6 Use In Software Compilers.- 15.7 Sequential Issues.- 15.8 Implementation Issues.- 15.9 Additional Challenges.- 15.10 Verification: Introduction.- 15.11 Static Timing.- 15.12 ATPG and SAT.- 15.13 BDDs.- 15.14 Equivalence Checking.- Appendices.- Appendix A: About the Authors.- Appendix B: Author Contact Information.

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