Logic Synthesis and Verification Algorithms

Author:   Gary D. Hachtel ,  Fabio Somenzi
Publisher:   Springer-Verlag New York Inc.
Edition:   Softcover reprint of the original 1st ed. 1996
ISBN:  

9781475770360


Pages:   564
Publication Date:   18 March 2013
Format:   Paperback
Availability:   Manufactured on demand   Availability explained
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Logic Synthesis and Verification Algorithms


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Overview

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. A unique feature of this text is the large collection of solved problems. Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

Full Product Details

Author:   Gary D. Hachtel ,  Fabio Somenzi
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   Softcover reprint of the original 1st ed. 1996
Dimensions:   Width: 17.80cm , Height: 3.10cm , Length: 25.40cm
Weight:   1.126kg
ISBN:  

9781475770360


ISBN 10:   1475770367
Pages:   564
Publication Date:   18 March 2013
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Paperback
Publisher's Status:   Active
Availability:   Manufactured on demand   Availability explained
We will order this item for you from a manufactured on demand supplier.

Table of Contents

A Quick Tour of Logic Synthesis with the Help of a Simple Example.- Two Level Logic Synthesis.- Boolean Algebras.- Synthesis of Two-Level Circuits.- Heuristic Minimization of Two-level Circuits.- Binary Decision Diagrams (BDDs).- Models of Sequential Systems.- Models of Sequential Systems.- Synthesis and Verification of Finite State Machines.- Finite Automata.- Multilevel Logic Synthesis.- Multi-Level Logic Synthesis.- Multi-Level Minimization.- Automatic Test Generation for Combinational Circuits.- Technology Mapping.

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