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OverviewScaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating conditions. Leakage is important in a variety of different contexts. For example, in desktop applications, active leakage power (i.e., leakage power when the processor is computing) is becoming significant compared to switching power. In battery operated systems, standby leakage (i.e., leakage when the processor clock is turned off) dominates as energy is drawn over long idle periods. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. It is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation techniques in nanometer technologies. This book provides an in-depth treatment of these issues for researchers and product designers. Full Product DetailsAuthor: Siva G. Narendra , Anantha P. ChandrakasanPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: Softcover reprint of hardcover 1st ed. 2006 Dimensions: Width: 15.50cm , Height: 1.70cm , Length: 23.50cm Weight: 0.492kg ISBN: 9781441938268ISBN 10: 1441938265 Pages: 308 Publication Date: 25 November 2010 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Out of print, replaced by POD  We will order this item for you from a manufatured on demand supplier. Table of ContentsTaxonomy of Leakage: Sources, Impact, and Solutions.- Leakage Dependence on Input Vector.- Power Gating and Dynamic Voltage Scaling.- Methodologies for Power Gating.- Body Biasing.- Process Variation and Adaptive Design.- Memory Leakage Reduction.- Active Leakage Reduction and Multi-Performance Devices.- Impact of Leakage Power and Variation on Testing.- Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors.- Case Study: Leakage Reduction in the Intel Xscale Microprocessor.- Transistor Design to Reduce Leakage.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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