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OverviewInterconnect Technology and Design for Gigascale Integration is the cumulative effort from academic researchers at Georgia Tech, MIT, and Stanford, as well as from industry researchers at IBM T.J. Watson Research Center, LSI Logic, and SUN microsystems. The material found in this book is unique in that it spans IC interconnect topics ranging from IBM's revolutionary copper process to an in depth exploration into interconnect-aware computer architectures. This broad swath of topics presented by leaders in the research field is intended to provide a comprehensive perspective on interconnect technology and design issues so that the reader will understand the implications of the semiconductor industry's next substantial milestone - gigascale integration. Full Product DetailsAuthor: Jeffrey A. Davis , James D. MeindlPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: Softcover reprint of the original 1st ed. 2003 Dimensions: Width: 15.50cm , Height: 2.20cm , Length: 23.50cm Weight: 0.652kg ISBN: 9781461350880ISBN 10: 1461350883 Pages: 411 Publication Date: 14 October 2012 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Manufactured on demand  We will order this item for you from a manufactured on demand supplier. Table of Contents1. Interconnect Opportunities for GSI.- 1.1 Introduction.- 1.2 The Interconnect Problem.- 1.3 Reverse Scaling.- 1.4 System-on-Chip.- 1.5 Three-Dimensional Integration.- 1.6 Input/Output Interconnect Enhancements.- 1.7 Photonic Interconnects.- 1.8 Conclusions.- 2. Copper BEOL Interconnects for Silicon CMOS Logic Technology.- 2.1 Introduction.- 2.2 BEOL Evolution.- 2.3 The Case for Copper.- 2.4 Electroplating of Cu.- 2.5 Reliability of Cu Interconnects.- 2.6 Processing of Cu Interconnects.- 2.7 Summary.- 3. Interconnect Parasitic Extraction of Resistance, Capacitance, and Inductance.- 3.1 Introduction.- 3.2 Electromagnetic Formulation.- 3.3 Resistance Extraction.- 3.4 Capacitance Extraction.- 3.5 Inductance Extraction.- 3.6 Summary.- 4. Distributed RC and RLC Transient Models.- 4.1 Introduction.- 4.2 Distributed RC Models.- 4.3 Distributed RLC Models.- 4.4 Non-Ideal Return Paths.- 4.5 Summary.- 5. Power, Clock, and Global Signal Distribution.- 5.1 Introduction.- 5.2 Global Signal Interconnect Modeling.- 5.3 Global Clock Distribution Modeling.- 5.4 Global Power Distribution Modeling.- 5.5 An Integrated Architecture for Global Interconnects.- 5.6 Conclusions.- 6. Stochastic Multilevel Interconnect Modeling and Optimization.- 6.1 Introduction.- 6.2 Wire-Length Distribution Model.- 6.3 Net Model Approximation.- 6.4 Comparisons with Actual Data.- 6.5 Critical Path Model.- 6.6 Dynamic Power Dissipation Model.- 6.7 Optimal n-Tier Multilevel Interconnect Architectures.- 6.8 Summary.- 7. Interconnect-Centric Computer Architectures.- 7.1 Introduction and Motivation.- 7.2 Interconnect-Aware Architectures.- 7.3 Interconnect Demand Models.- 7.4 Related Work.- 7.5 GENESYS Organization and Models.- 7.6 Heterogeneous Architecture Models.- 7.7 System Design Analysis.- 7.8 Wire Demands andtheir Relation to Architecture.- 7.9 Conclusion.- 8. Chip-to-Module Interconnect.- 8.1 Introduction.- 8.2 Packaging and Chip-to-Module Trends.- 8.3 Microvia Printed Wiring Board Technologies.- 8.4 Chip-to-Module Interconnections for GSI.- 9. 3-D ICs DSM Interconnect Performance Modeling and Analysis.- 9.1 Introduction.- 9.2 Motivation for 3-D ICs.- 9.3 Scope of This Study.- 9.4 Area and Performance Estimation of 3-D ICs.- 9.5 Challenges for 3-D ICs.- 9.6 mplications for Circuit Design and System-on-a-Chip Applications.- 9.7 Overview of 3-D IC Technology.- 9.8 Conclusions.- 10. Silicon Microphotonics.- 10.1 Introduction.- 10.2 Optical Interconnection.- 10.3 Monolithic Silicon Microphotonics.- 10.4 Optical Clock Distribution and Data I/O.- 10.5 Summary.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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