Overview

In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design. Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design. The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.

Full Product Details

Author:   Jari Nurmi ,  H. Tenhunen ,  J. Isoaho ,  Axel Jantsch
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   1st ed. Softcover of orig. ed. 2004
Dimensions:   Width: 16.00cm , Height: 3.00cm , Length: 24.00cm
Weight:   0.732kg
ISBN:  

9781441954428

ISBN 10:   1441954422
Pages:   454
Publication Date:   04 November 2010
Audience:   Professional and scholarly ,  Professional and scholarly ,  College/higher education ,  Professional & Vocational ,  Professional & Vocational
Format:   Paperback
Publisher's Status:   Active
Availability:   In Print  
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Table of Contents

Physical and Electrical Issues.- System-on-Chip-Challenges in the Deep-Sub-Micron Era.- Wires as Interconnects.- Global Interconnect Analysis.- Design Methodologies for on-Chip Inductive Interconnect.- Clock Distribution for High Performance Designs.- Logical and Architectural Issues.- Error-Tolerant Interconnect Schemes.- Power Reduction Coding for Buses.- Bus Structures in Network-on-Chips.- From Buses to Networks.- Arbitration and Routing Schemes for on-Chip Packet Networks.- Design Methodology and Tools.- Self-Timed Approach for Noise Reduction in NoC Reduction in NoC.- Formal Communication Modeling and Refinement.- Network-Centric System-Level Model for Multiprocessor Soc Simulation.- Socket-Based Design Using Decoupled Interconnects.- Application Cases.- Interconnect and Memory Organization in SOCs for Advanced Set-Top Boxes and TV.- A Brunch from the Coffee Table-Case Study in NoC Platform Design.

Reviews

From the reviews: ...a collection of edited chapters written by various experts on NoC and on-chip communications design; the editors contributed to several of the chapters and, for the others, drew on several colleagues-including those participating in Complain, the Finnish-Swedish Excite research project. The editors have carefully chosen the topics in this volume to reflect the multiple levels and types of design knowledge required to gain an appreciation of the field... this book is quite useful for educating any SoC design team in many of the areas critical to adapting their designs to future generations of interconnect. It can also be a useful reference text for advanced undergraduate- and graduate-level courses in SoC and VLSI design. Designers and design educators should take a close look at this book. (IEEE Design & Test of Computers Magazine) The book is a collection of edited chapters written by various experts on NoC and on chip communications design ... . The editors have carefully chosen the topics in this volume ... . Clearly, the book covers an impressive breadth of topics ... . Each chapter surveys the relevant literature in its particular topic area and provides an extensive reference list ... . a useful reference text for advanced undergraduate- and graduate-level courses in SoC and VLSI design. Design and design educators should take a close look at this book. (Grant Martin, IEEE Design & Test of Computers, March-April, 2005)

From the reviews: !a collection of edited chapters written by various experts on NoC and on-chip communications design; the editors contributed to several of the chapters and, for the others, drew on several colleagues--including those participating in Complain, the Finnish-Swedish Excite research project. The editors have carefully chosen the topics in this volume to reflect the multiple levels and types of design knowledge required to gain an appreciation of the field! this book is quite useful for educating any SoC design team in many of the areas critical to adapting their designs to future generations of interconnect. It can also be a useful reference text for advanced undergraduate- and graduate-level courses in SoC and VLSI design. Designers and design educators should take a close look at this book. (IEEE Design & Test of Computers Magazine) The book is a collection of edited chapters written by various experts on NoC and on chip communications design ! . The editors have carefully chosen the topics in this volume ! . Clearly, the book covers an impressive breadth of topics ! . Each chapter surveys the relevant literature in its particular topic area and provides an extensive reference list ! . a useful reference text for advanced undergraduate- and graduate-level courses in SoC and VLSI design. Design and design educators should take a close look at this book. (Grant Martin, IEEE Design & Test of Computers, March-April, 2005)

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