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OverviewThis book raises the level of understanding of thermal design criteria. It provides the design team with sufficient knowledge to help them evaluate device architecture trade-offs and the effects of operating temperatures. The author provides readers a sound scientific basis for system operation at realistic steady state temperatures without reliability penalties. Higher temperature performance than is commonly recommended is shown to be cost effective in production for life cycle costs.The microelectronic package considered in the book is assumed to consist of a semiconductor device with first-level interconnects that may be wirebonds, flip-chip, or tape automated bonds; die attach; substrate; substrate attach; case; lid; lid seal; and lead seal. The temperature effects on electrical parameters of both bipolar and MOSFET devices are discussed, and models quantifying the temperature effects on package elements are identified. Temperature-related models have been used to derive derating criteria for determining the maximum and minimum allowable temperature stresses for a given microelectronic package architecture.T he first chapter outlines problems with some of the current modeling strategies. The next two chapters present microelectronic device failure mechanisms in terms of their dependence on steady state temperature, temperature cycle, temperature gradient, and rate of change of temperature at the chip and package level. Physics-of-failure based models used to characterize these failure mechanisms are identified and the variabilities in temperature dependence of each of the failure mechanisms are characterized. Chapters 4 and 5 describe the effects of temperature on the performance characteristics of MOS and bipolar devices. Chapter 6 discusses using high-temperature stress screens, including burn-in, for high-reliability applications. The burn-in conditions used by some manufacturers are examined and a physics-of-failure approach is described. The final chapter overviews existing guidelines for thermal derating of microelectronic devices, which presently involve lowering the junction temperature. The reader then learns how to use physics-of-failure models presented in the previous chapters for various failure processes, to evaluate the sensitivity of device life to variations in manufacturing defects, device architecture, temperature, and non-temperature stresses. Full Product DetailsAuthor: Pradeep Lall , Michael G. Pecht , Edward B. HakimPublisher: Taylor & Francis Inc Imprint: CRC Press Inc Dimensions: Width: 17.80cm , Height: 2.10cm , Length: 25.40cm Weight: 0.975kg ISBN: 9780849394508ISBN 10: 0849394503 Pages: 328 Publication Date: 24 April 1997 Audience: College/higher education , Professional and scholarly , Postgraduate, Research & Scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsDoes the Cooling of Electronics Increase Reliability? Temperature Dependence of Microelectronic Package Failure Mechanisms Temperature Dependencies of Failure Mechanisms in the Die Metallization Effect of Hydrogen (H2) and Helium (He) Ambients On Metallization Versus Temperature Temperature Dependencies of Failure Mechanisms in the Device Oxide Temperature Dependencies of Failure Mechanisms in the Device Temperature Dependencies of Failure Mechanisms in the Device Oxide Interface Temperature Dependence of Microelectronic Package Failure Mechanisms Temperature Dependencies of Failure Mechanisms in the Die and Die/Substrate Attach Temperature Dependencies of Failure Mechanisms in First-Level Interconnections Temperature Dependencies of Failure Mechanisms in the Package Case Electrical Parameter Variations in Bipolar Devices Introduction Temperature Dependence of Bipolar Junction Transistor Parameters Electrical Parameter Variations in Mosfet Devices Temperature Dependence of Mosfet Parameters A Physics-of-Failure Approach to IC Burn-In Introduction Burn-In Philosophy Problems with Present Approach to Burn-In A Physics-of-Failure Approach to Burn-In Derating Guidelines for Temperature-Tolerant Design of Microelectronic Devices Introduction Problems with the Present Approach to Device Derating A Physics-of-Failure Approach to Device Derating Derating for Failure Mechanisms in Die Metallization Derating Guidelines for Temperature-Tolerant Design of Electronic Packages Derating for Failure Mechanisms in the Die and Die/Substrate Attach Derating for Failure Mechanisms in the First-Level Interconnects Derating for Failure Mechanisms in the Package Case A Guide for Steady State Temperature EffectsReviewsAuthor InformationLall, Pradeep; Pecht, Michael; Hakim, Edward B. Tab Content 6Author Website:Countries AvailableAll regions |
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