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OverviewThis work is a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips. The text is organized in 11 chapters as follows: chapter one provides an overview to the design of clock networks; chapter two specifies the timing requirements in digital design; chapter two shows the circuits of sequential elements including latches and flip-flops; chapter four describes the domino circuits, which need special clock signals; chapter five discusses the phase-locked loop (PLL) and delay-locked loop (DLL), which provide the clock generation and de-skewing for the on-chip clock distribution; chapter 6 summarizes the clock distribution techniques published in the state-of-the-art microprocessor chips; chapter 7 describes the CAD flow on the clock network simulation; chapter 8 gives the research work on low-voltage swing clock distribution; chapter 9 explores the possibility of placing the global clock tree on the package layers; chapter 10 shows the algorithms of balanced clock routing and wire sizing for the skew minimization; and chapter 11 shows a commercial CAD tool that deals with clock tree synthesis in the ASIC design flow. Full Product DetailsAuthor: Qing K. ZhuPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: 2003 ed. Dimensions: Width: 15.60cm , Height: 1.20cm , Length: 23.40cm Weight: 1.020kg ISBN: 9781402073465ISBN 10: 1402073461 Pages: 188 Publication Date: 31 December 2002 Audience: College/higher education , Professional and scholarly , Undergraduate , Postgraduate, Research & Scholarly Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of Contents1 Introduction.- 2 Overview to Timing Constraints.- 3 Sequential Clocked Elements.- 4 Design Methodology for Domino Circuits.- 5 Clock Generation and De-Skewing.- 6 Microprocessor Clock Distribution Examples.- 7 Clock Network Simulation Methods.- 8 Low-Voltage Swing Clock Distribution.- 9 Routing Clock on Package.- 10 Balanced Clock Routing Algorithms.- 11 Clock Tree Design Flow in Asic.- Reference.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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