Overview

High-Performance Digital VLSI Circuit Design is the first book devoted entirely to the design of digital high-performance VLSI circuits. CMOS, BiCMOS and bipolar ciruits are covered in depth, including state-of-the-art circuit structures. Recent advances in both the computer and telecommunications industries demand high-performance VLSI digital circuits. Digital processing of signals demands high-speed circuit techniques for the GHz range. The design of such circuits represents a great challenge; one that is amplified when the power supply is scaled down to 3.3 V. Moreover, the requirements of low-power/high-performance circuits adds an extra dimension to the design of such circuits. High-Performance Digital VLSI Circuit Design is a self-contained text, introducing the subject of high-performance VLSI circuit design and explaining the speed/power tradeoffs. The first few chapters of the book discuss the necessary background material in the area of device design and device modeling, respectively. High-performance CMOS circuits are then covered, especially the new all-N-logic dynamic circuits. Propagation delay times of high-speed bipolar CML and ECL are developed analytically to give a thorough understanding of various interacting process, device and circuit parameters. High-current phenomena of bipolar devices are also addressed as these devices typically operate at maximum currents for limited device area. Different, new, high-performance BiCMOS circuits are presented and compared to their conventional counterparts. These new circuits find direct applications in the areas of high-speed adders, frequency dividers, sense amplifiers, level-shifters, input/output clock buffers and PLLs. The book concludes with a few system application examples of digital high-performance VLSI circuits. Audience: A vital reference for practicing IC designers. Can be used as a text for graduate and senior undergraduate students in the area.

Full Product Details

Author:   Richard X. Gu ,  Khaled M. Sharaf ,  Mohamed I. Elmasry
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   Softcover reprint of the original 1st ed. 1996
Volume:   338
Dimensions:   Width: 15.50cm , Height: 1.80cm , Length: 23.50cm
Weight:   0.528kg
ISBN:  

9781461359708

ISBN 10:   1461359708
Pages:   320
Publication Date:   08 October 2012
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Paperback
Publisher's Status:   Active
Availability:   Manufactured on demand  
We will order this item for you from a manufactured on demand supplier.

Table of Contents

1 Introduction.- 1.1 Comparisons Between Bipolar and MOS Transistors.- 1.2 CMOS Digital Circuits.- 1.3 Bipolar ECL Circuits.- 1.4 BiCMOS Circuits.- 1.5 Power-Delay Tradeoffs Between CMOS, Bipolar ECL and BiCMOS Circuits.- 1.6 Book Organization.- References.- 2 Device Design Considerations.- 2.1 Design Considerations for MOSFETs.- 2.2 Design Considerations for Bipolar Transistors.- 2.3 Cutoff Frequency.- 2.4 BiCMOS Device Design Considerations.- 2.5 BiCMOS Device Scaling.- 2.6 Chapter Summary.- References.- 3 Device Modeling.- 3.1 Modeling of the MOS Transistor.- 3.2 Modeling of the Bipolar Transistor.- 3.3 Chapter Summary.- References.- 4 Cmos High-Performance Circuits.- 4.1 Static Digital CMOS Circuits.- 4.2 Non-Pipelined Dynamic CMOS Circuits.- 4.3 Pipelined Dynamic CMOS Circuits.- 4.4 An All-N-Logic Single-Phase Pipelined Dynamic CMOS Logic.- 4.5 Chapter Summary.- References.- 5 A Cml Propagation Delay Model.- 5.1 Introduction.- 5.2 CML and ECL Previous Delay Models.- 5.3 New CML Propagation Delay Model.- 5.4 Transient Analysis.- 5.5 High-Current Effects.- 5.6 Model Verification and Its Application in Circuit Optimization.- 5.7 Model Limitations.- 5.8 Chapter Summary.- References.- 6 Series-Gated Cml and Ecl Bipolar Circuits.- 6.1 Introduction.- 6.2 Two-level Series-gating CML and ECL Circuit Design.- 6.3 Analysis and Optimization of Two-level Circuits.- 6.4 Series-Gated CML and ECL Circuits.- 6.5 Results and Model Verification.- 6.6 Model Applications in Optimizing CML and ECL Series- Gated High-Speed Circuits.- 6.7 Chapter Summary.- References.- 7 High-Performance Bicmos Circuit Structures.- 7.1 Introduction.- 7.2 ECL/CMOS Interface Circuits.- 7.3 Dynamic ECL Reference Voltage (DRV) CMOS/ECL Interface Circuits.- 7.4 BiCMOS Sense Amplifiers for SRAM.- 7.5 Chapter Summary.- References.- 8 High-performance Cml, Ecl and Ntl Bicmos Circuits.- 8.1 Introduction.- 8.2 Low-Power Circuits and Systems.- 8.3 BJT and MOS Series-Gated CML Circuit Techniques.- 8.4 Performance of XOR, D-latch BJT and MOS Series-Gated Circuits.- 8.5 Performance of CML D-Latch Comparator Circuits.- 8.6 High-Performance ECL Circuit Techniques.- 8.7 Active Load (Series Diode and Resistor).- 8.8 Active-Pull-Down Techniques.- 8.9 Discussion and Assessment of Active-Pull-Down ECL Cir-cuit Techniques.- 8.10 BiCMOS Active-Pull-Down ECL Circuit Technique.- 8.11 Non-Threshold-Logic Circuits.- 8.12 Conventional NTL Circuits.- 8.13 APD-NTL Circuit Techniques.- 8.14 APD-NTL Circuit Performance.- 8.15 Applications.- 8.16 Chapter Summary.- References.- 9 High-Performance System Applications.- 9.1 Introduction.- 9.2 Phase-Locked Loops.- 9.3 Phase-Locked Loop Building Blocks.- 9.4 Chapter Summary.- References.- A Appendix.- B Appendix.

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