High-Performance Computing on the Intel® Xeon Phi™: How to Fully Exploit MIC Architectures

Author:   Endong Wang ,  Qing Zhang ,  Bo Shen ,  Guangyong Zhang
Publisher:   Springer International Publishing AG
Edition:   Softcover reprint of the original 1st ed. 2014
ISBN:  

9783319358796


Pages:   338
Publication Date:   01 October 2016
Format:   Paperback
Availability:   In Print   Availability explained
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High-Performance Computing on the Intel® Xeon Phi™: How to Fully Exploit MIC Architectures


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Author:   Endong Wang ,  Qing Zhang ,  Bo Shen ,  Guangyong Zhang
Publisher:   Springer International Publishing AG
Imprint:   Springer International Publishing AG
Edition:   Softcover reprint of the original 1st ed. 2014
Dimensions:   Width: 15.50cm , Height: 1.90cm , Length: 23.50cm
Weight:   5.504kg
ISBN:  

9783319358796


ISBN 10:   3319358790
Pages:   338
Publication Date:   01 October 2016
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Paperback
Publisher's Status:   Active
Availability:   In Print   Availability explained
This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us.

Table of Contents

Part 1: Fundamental Concepts of MIC.- 1 High-performance Computing( HPC) with MIC.- 2 MIC Hardware and Software Architecture.- 3 The First MIC Example—Computing Pi.- 4 Fundamentals of Open MP and MPI Programming.- 5 MIC Programming.- 6 Debugging and Profiling Tools for MIC.- 7 Intel MIC MKL Library.- Part 2: Performance Optimization.- 8 Performance Optimization on MIC.- 9 MIC Optimization Example: Matrix Multiplication.- Part 3: Project Development.- 10 Developing HPC Applications Based on the MIC.- 11 HPC Applications Based on MIC.

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Author Information

Endong Wang is the Director of the State Key Laboratory of High-Efficiency Server and Storage Technology at the Inspur-Intel China Parallel Computing Joint Lab and Senior Vice President of the Inspur Group Co., Ltd. Qing Zhang is the lead engineer of the Inspur-Intel China Parallel Computing Joint Lab and with his team he was among the first to work with the development environment of the Intel® Xeon processor and Intel® Xeon Phi™ coprocessor. Together they have several years of experience in HPC programming.

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