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OverviewFull Product DetailsAuthor: Mike Tien-Chien LeePublisher: Artech House Publishers Imprint: Artech House Publishers Edition: Unabridged edition Dimensions: Width: 15.80cm , Height: 1.80cm , Length: 22.00cm Weight: 0.490kg ISBN: 9780890069073ISBN 10: 0890069077 Pages: 240 Publication Date: 31 January 1997 Audience: Professional and scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: Out of stock  The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available. Table of ContentsBackground. Sequential Depth Reduction During Allocation. Sequential Loop Reduction During Allocation. Testability Synthesis During Scheduling. Conditional Resource Sharing for Testability. State-of-the-Art High-Level Test Synthesis.ReviewsAuthor InformationDr. Mike Tien-Chien Lee is a software engineer at Avant! Corp. He holds a Ph.D. in electrical engineering from Princeton University. Dr. Lee serves on program committees of IEEE International Test Synthesis Workshop. He received Best Paper Awards at the Asia and South Pacific Design Automation Conference (ASP-DAC) in 1995, and the IEEE/ACM Design Automation Conference (DAC) in 1996. Tab Content 6Author Website:Countries AvailableAll regions |
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