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OverviewThe drive toward smaller and smaller electronic componentry has huge implications for the materials currently being used. As quantum mechanical effects begin to dominate, conventional materials will be unable to function at scales much smaller than those in current use. For this reason, new materials with higher electrical permittivity will be required, making this is a subject of intensive research activity within the microelectronics community. High k Gate Dielectrics reviews the state-of-the-art in high permittivity gate dielectric research. Consisting of contributions from leading researchers from Europe and the USA, the book first describes the various deposition techniques used for construction of layers at these dimensions. It then considers characterization techniques of the physical, chemical, structural, and electronic properties of these materials. The book also reviews the theoretical work done in the field and concludes with technological applications. Full Product DetailsAuthor: Michel HoussaPublisher: Taylor & Francis Ltd Imprint: CRC Press Weight: 0.453kg ISBN: 9780367454449ISBN 10: 0367454440 Pages: 614 Publication Date: 18 December 2020 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsIntroduction The need for high-k gate dielectrics and materials requirement Deposition techniques ALCVD, MOCVD, PLD, MBE Characterization Physico-chemical characterization X-ray and electron spectroscopies Oxygen diffusion and thermal stability Defect characterization by ESR Band alignment determined by photo-injection Electrical characteristics Theory of defects in high-k materials Bonding constraints and defect formation at Si/high-k interfaces Band alignment calculations Electron mobility at the Si/high-k interface Model for defect generation during electrical stress Technological aspects Device integration issues Device concepts for sub-100 nm CMOS technologies Transistor characteristics Nonvolatile memories based on high-k ferroelectric layersReviewsAuthor InformationMichel Houssa Laboratoire Materiaux et Microelectronique de Provence, Universite de Provence, France Silicon Processing and Device Technology Division, IMEC, Belgium Tab Content 6Author Website:Countries AvailableAll regions |
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