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OverviewRecently, there has been a trend toward processors based on the RISC (Reduced Instruction Set Computer) design. This is an accessible and all-encompassing compendium on RISC processors, introducing five of them: MIPS, SPARC, PowerPC, ARM, and Intel's 64-bit Itanium. Initial chapters explain differences between the CISC and RISC designs, and the core RISC design principles are clearly discussed. Later chapters provide instruction on MIPS assembly language programming, so that readers can readily learn the concepts and principles introduced earlier. Professionals, programmers, and students in computer architecture and programming courses will find the guide an essential resource. Full Product DetailsAuthor: Sivarama P. DandamudiPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: 2005 ed. Dimensions: Width: 17.80cm , Height: 2.30cm , Length: 25.40cm Weight: 2.020kg ISBN: 9780387210179ISBN 10: 0387210172 Pages: 388 Publication Date: 16 February 2005 Audience: Professional and scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: Out of print, replaced by POD  We will order this item for you from a manufatured on demand supplier. Table of ContentsOverview.- Processor Design Issues.- RISC Principles.- Architectures.- MIPS Architecture.- SPARC Architecture.- PowerPC Architecture.- Itanium Architecture.- ARM Architecture.- MIPS Assembly Language.- SPIM Simulator and Debugger.- Assembly Language Overview.- Procedures and the Stack.- Addressing Modes.- Arithmetic Instructions.- Conditional Execution.- Logical and Shift Operations.- Recursion.- Floating-Point Operations.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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