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OverviewAt 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture. In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability. Full Product DetailsAuthor: Tsung-Yi Ho , Yao-Wen Chang , Sao-Jie ChenPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: 2007 ed. Dimensions: Width: 15.50cm , Height: 0.70cm , Length: 23.50cm Weight: 0.780kg ISBN: 9781402061943ISBN 10: 1402061943 Pages: 102 Publication Date: 21 August 2007 Audience: College/higher education , Professional and scholarly , Undergraduate , Postgraduate, Research & Scholarly Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsRouting Challenges for Nanometer Technology.- Multilevel Full-Chip Routing Considering Crosstalk And Performance.- Multilevel Full-Chip Routing Considering Antenna Effect Avoidance.- Multilevel Full-Chip Routing For The X-Based Architecture.- Concluding Remarks And Future Work.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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