Overview

Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield. Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing. This volume focuses on the core of the interface between manufacturing and testing - the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems. Failure mechanism models are developed and presented which can be used to accurately estimate the probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modelling and design manufacturing.

Full Product Details

Author:   Jitendra B. Khare ,  Wojciech Maly
Publisher:   Springer
Imprint:   Springer
Edition:   1996 ed.
Volume:   5
Dimensions:   Width: 15.50cm , Height: 1.10cm , Length: 23.50cm
Weight:   0.930kg
ISBN:  

9780792397144

ISBN 10:   0792397142
Pages:   150
Publication Date:   30 April 1996
Audience:   General/trade ,  Professional and scholarly ,  Professional & Vocational
Format:   Hardback
Publisher's Status:   Active
Availability:   In Print  
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Table of Contents

1. Introduction.- 1.1 Trends in IC Manufacturing.- 1.2 Yield Loss Mechanisms in ICs.- 1.3 Functional Yield Estimation.- 1.4 Research Goals.- 1.5 Outline.- 1.6 References.- 2. Background.- 2.1 Terminology.- 2.2 Point Model.- 2.3 Disk Model.- 2.4 Experimental Investigation of the Disk Model.- 2.5 Summary.- 2.6 References.- 3. Contamination-Defect-Fault (CDF) Simulation.- 3.1 New Contamination Model.- 3.2 Contamination-Defect-Fault (CDF) Simulation.- 3.3 References.- 4. CDF Mapper CODEF.- 4.1 CODEF - An Overview.- 4.2 Chip Data Base (CDB).- 4.3 Process Models.- 4.4 Circuit Extraction.- 4.5 Netlist Comparison.- 4.6 CODEF - Illustration.- 4.7 Runtime and Memory Usage.- 4.8 References.- 5. CODEF - Applications.- 5.1 Yield Estimation.- 5.2 Fault Modeling.- 5.3 Failure Analysis.- 5.4 References.- 6. Possible Extensions.- 6.1 CODEF Speed and Memory Considerations.- 6.2 Addition of New Process Models.- 6.3 Additional Contamination Properties.- 6.4 Extraction of Bipolar Transistors.- 6.5 Identification of Contamination Parameters.- 6.6 References.- 7. Conclusion.- Appendix A: CMOS Process Flow.

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