Overview

This book shows how the layout of an analog circuit can be automatically generated in a fully open-source way. Based on an exemplary design flow, it introduces and explains the necessary steps for transforming a SPICE netlist into a layout, which can be inspected by the open-source layout editor Magic VLSI. This is done by using the industry’s first open-source process design kit SKY130. Furthermore, the implementation of the design flow in the programming language Python is available as open-source on GitHub.  ​​​​​​​

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9783031685613

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Jakob Ratschenberger has received his Bachelor of Science (BSc) in the field of Electronics and Information Technology, from the Johannes Kepler University Linz, Austria, in 2022. He received the Dipl.-Ing. degree (with distinction) in Electronics and Information Technology from the Johannes Kepler University Linz, Austria, in 2024. Harald Pretl received a Dipl.-Ing. degree (with distinction) in electrical engineering from the Graz University of Technology, Austria, in 1997, and the Dr. techn. degree from the Johannes Kepler University (JKU) in Linz, Austria, in 2001. From 2000 to 2011, he worked at Infineon Technologies as Director and Senior Principal Engineer, from 2011 to 2019 at Intel as Senior Principal Engineer and Chief RF Technologist, and from 2019 to 2022 at Apple, contributing to several generations of cellular RF transceivers. Since 2015, he has been a full professor, heading the Institute for Integrated Circuits (IIC) at JKU. He maintains the IIC-OSIC-TOOLS and is a member of the IEEE SSCS TC-OSE. In 2023, Harald founded PRETL consult GmbH, providing consulting services in the area of IC design.

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