Overview

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions. Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

Full Product Details

Author:   Kothanda Umamageswaran ,  Sheetanshu L. Pandey ,  Philip A. Wilsey
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   Softcover reprint of the original 1st ed. 1999
Dimensions:   Width: 15.50cm , Height: 0.90cm , Length: 23.50cm
Weight:   0.290kg
ISBN:  

9781461373315

ISBN 10:   146137331
Pages:   158
Publication Date:   26 October 2012
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Paperback
Publisher's Status:   Active
Availability:   Manufactured on demand  
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Table of Contents

1. Introduction.- 1.1 Goals of the Work.- 1.2 Scope of the Work.- 1.3 Notation.- 1.4 Overview of Book.- 2. Related Work.- 2.1 Higher Order Logic.- 2.2 Denotational Semantics.- 2.3 Functional Semantics.- 2.4 Axiomatic Semantics.- 2.5 Petri Nets.- 2.6 Evolving Algebras.- 2.7 Boyer-Moore Logic.- 2.8 Summary.- 3. The Static Model.- 3.1 The VHDL World.- 3.2 Signals.- 3.3 Variables.- 3.4 The Port Hierarchy.- 3.5 Data Types.- 3.6 Expressions.- 3.7 Subprograms.- 3.8 Sequential Statements.- 3.9 Concurrent Statements.- 3.10 Summary.- 4. A Well-Formed VHDL Model.- 4.1 Signals.- 4.2 Variables.- 4.3 The Port Hierarchy.- 4.4 Data Types.- 4.5 Expressions.- 4.6 Sequential Statements.- 4.7 Concurrent Statements.- 4.8 Summary.- 5. The Reduction Algebra.- 5.1 Signal Assignment Statements.- 5.2 Concurrent Statements.- 5.3 The Reduced Form.- 6. Completeness of the Reduced Form.- 6.1 A Brief Overview of PVS.- 6.2 The Specification of the Reduction Algebra in PVS.- 6.3 Signal Assignment Reduction.- 6.4 Completeness.- 6.5 Irreducibility.- 6.6 Conclusion.- 7. Interval Temporal Logic.- 8. The Dynamic Model.- 8.1 Methodology.- 8.2 Evaluation of VHDL Statements.- 8.3 Transaction Lists.- 8.4 The State Space.- 8.5 Waveforms.- 8.6 Observability.- 8.7 Attributes.- 8.8 Conclusions.- 9. Applications of the Dynamic Model.- 9.1 Similarity Revisited.- 9.2 Process Folding.- 9.3 Signal Collapsing.- 9.4 Elimination of Marking.- 9.5 Summary.- 10. A Framework for Proving Equivalences using PVS.- 10.1 The Dynamic Model.- 10.2 Validation of the Semantics.- 10.3 Developing Proofs of Optimizations.- 10.4 Applications to Practical Use.- 11. Conclusions.- 11.1 Contributions of this research.- 11.2 Future Work.- Appendices A—.- A.1 The relation during(b,a) holds.- A.2 The relation finishes(b,a) holds.- A.3 Therelation overlaps(a,b) holds.- References.

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