Efficient Branch and Bound Search with Application to Computer-Aided Design

Author:   Xinghao Chen ,  Michael L. Bushnell
Publisher:   Springer
Edition:   1996 ed.
Volume:   4
ISBN:  

9780792396734


Pages:   146
Publication Date:   31 December 1995
Format:   Hardback
Availability:   In Print   Availability explained
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Efficient Branch and Bound Search with Application to Computer-Aided Design


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Overview

Branch-and-bound search has been known for a long time and has been widely used in solving a variety of problems in computer-aided design (CAD) and many important optimization problems. In many applications, the classic branch-and-bound search methods perform duplications of computations, or rely on the search decision trees which keep track of the branch-and-bound search processes. In CAD and many other technical fields, the computational cost of constructing branch-and-bound search decision trees in solving large-scale problems is prohibitive and duplications of computations are intolerable. Efficient branch-and-bound methods are needed to deal with today's computational challenges. Efficient branch-and-bound methods must not duplicate computations. This volume describes an efficient branch-and-bound method for logic justification, which is fundamental to automatic test pattern generation (ATPG), redundancy identification, logic synthesis, minimization, verification and other problems in CAD. The method is called justification equivalence, based on the observation that justification processes may share identical subsequent search decision sequences. With justification equivalence, duplication of computations is avoided in the dynamic branch-and-bound search process without using search decision trees. This book consists of two parts. The first part, containing the first three chapters, provides the theoretical work. The second part deals with applications, particularly ATPG for sequential circuits. This book is intended, in particular, for those readers who are interested in the design and testing of digital circuits.

Full Product Details

Author:   Xinghao Chen ,  Michael L. Bushnell
Publisher:   Springer
Imprint:   Springer
Edition:   1996 ed.
Volume:   4
Dimensions:   Width: 15.60cm , Height: 1.10cm , Length: 23.40cm
Weight:   0.910kg
ISBN:  

9780792396734


ISBN 10:   0792396731
Pages:   146
Publication Date:   31 December 1995
Audience:   College/higher education ,  Professional and scholarly ,  Postgraduate, Research & Scholarly ,  Professional & Vocational
Format:   Hardback
Publisher's Status:   Active
Availability:   In Print   Availability explained
This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us.

Table of Contents

I Theory.- 1 Introduction.- 1.1 Branch-and-Bound Search.- 1.2 Efficient Branch-and-Bound Search.- 1.3 Justification with Branch-and-Bound.- 1.4 Why Use Justification Equivalence?.- 1.5 Prior Work.- 1.6 Organization of the Book.- 2 Justification Equivalence.- 2.1 Introduction.- 2.2 Justification Decomposition.- 2.3 Properties.- 2.4 Identification of Shared Justification Decisions.- 2.5 Justification Equivalence.- 2.6 Efficient Representation.- 2.7 An ATPG Example.- 2.8 Summary.- 3 Justification in Finite State Space.- 3.1 Introduction.- 3.2 What is State Justification?.- 3.3 Justifiability of States.- 3.4 State Justification Equivalence.- 3.5 Covering Properties.- 3.6 An Example.- 3.7 Summary.- II Applications.- 4 Sequential Circuit Test Generation.- 4.1 Introduction.- 4.2 What is Sequential Circuit Test Generation?.- 4.3 Complexity of Test Generation.- 4.4 How Can Justification Equivalence Help?.- 4.5 Prior Work.- 5 Fault Effects.- 5.1 Introduction.- 5.2 Fault Effect Analysis.- 5.3 Summary.- 6 The Sest Algorithm.- 6.1 Introduction.- 6.2 The Control Flow.- 6.3 Complexity of Retrieval.- 6.4 Implementation.- 6.5 Summary.- 7 Experimental Results.- 7.1 Introduction.- 7.2 Experimental Procedures.- 7.3 ATPG Time Proportions.- 7.4 SEST Efficiency Evaluation.- 7.5 Benchmark Results.- 7.6 Summary.- 8 Redundancy Identification.- 8.1 Introduction.- 8.2 Why is Redundancy Identification Needed?.- 8.3 Prior Work.- 8.4 Efficient Redundancy Identification.- 8.5 Summary.- 9 Logic Verification.- 9.1 Introduction.- 9.2 Prior Work.- 9.3 Logic Verification via Test Generation.- 9.4 Summary.- 10 Conclusion.- A Sest User’s Guide.- A.1 Introduction.- A.2 Command Synopsis.- A.3 Options.- A.4 Inputs and Outputs.- A.5 Output Files.- A.6 Example.- A.7 Down-Loading SEST from the Disk.- A.8 Reporting Bugs.- A.9 Author.- References.

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