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OverviewFull Product DetailsAuthor: Louis Scheffer (Cadence Design Systems, San Jose, California, USA) , Luciano Lavagno (Cadence Berkeley Laboratories, California, USA) , Grant Martin (Tensilica Inc., Santa Clara, California, USA) , Luciano Lavagno (Cadence Berkeley Laboratories, California, USA)Publisher: Taylor & Francis Inc Imprint: CRC Press Inc Dimensions: Width: 17.80cm , Height: 3.40cm , Length: 25.40cm Weight: 1.111kg ISBN: 9780849379239ISBN 10: 0849379237 Pages: 544 Publication Date: 23 March 2006 Audience: Professional and scholarly , Professional and scholarly , Professional & Vocational , Postgraduate, Research & Scholarly Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsIntroduction. The IC Design Process and EDA. Tools and Methodologies for System-Level Design. System-level specification and modeling languages. SoC Block Based Design and IP Assembly. Performance Evaluation Methods for MPSoC Design. Processor Modeling and Design Tools. Embedded Software Modeling and Design. Using Performance Metrics to Select Microprocessor Cores for IC Designs. Parallelizing High-Level Synthesis: A Code Transformational Approach to High-Level Synthesis. Cycle-Accurate System-Level Modeling and Performance Evaluation. Micro-Architectural Power Estimation and Optimization. Design Planning. Design and Verification Languages. Digital Simulation. Using Transactional Level Models in a SoC Design Flow. Assertion-based verification. Hardware Acceleration and Emulation. Formal Property Verification. Design for Test. Automatic Test Pattern Generation. Analog and Mixed-Signal Test.ReviewsAuthor InformationLouis Scheffer, Luciano Lavagno, Grant Martin Tab Content 6Author Website:Countries AvailableAll regions |
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