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OverviewThis title covers the subject of digital systems design using two important technologies: Field Programmable Logic Devices (FPLDs) and Hardware Description Languages (HDLs). These two technologies are combined to aid in the design, prototyping, and implementation of a whole range of digital systems from very simple ones replacing traditional glue logic to very complex ones customized as the applications require. Three HDLs are presented: VHDL and Verilog, the widely used standard languages, and the proprietary Altera HDL (AHDL). The chapters on these languages serve as tutorials and comparisons are made that show the strengths and weaknesses of each language. A large number of examples are used in the description of each language providing insight for the design and implementation of FPLDs. The CD-ROM included with the book contains the Altera MAX+PLUS II development environment which is ready to compile and simulate all examples. With the addition of the Altera UP-1 prototyping board, all examples can be tested and verified in a real FPLD. Full Product DetailsAuthor: Zoran Salcic , Asim SmailagicPublisher: Springer Imprint: Springer Edition: 2nd ed. 2000 Dimensions: Width: 15.50cm , Height: 3.40cm , Length: 23.50cm Weight: 1.216kg ISBN: 9780792379201ISBN 10: 0792379209 Pages: 621 Publication Date: 31 October 2000 Audience: College/higher education , Professional and scholarly , Undergraduate , Postgraduate, Research & Scholarly Format: Hardback Publisher's Status: Active Availability: Out of print, replaced by POD  We will order this item for you from a manufatured on demand supplier. Table of Contentsto Field Programmable Logic Devices.- Examples of Major FPLD Families.- Design Tools and Logic Design with FPLDS.- to Design Using AHDL.- Advanced AHDL.- Design Examples.- Simp-Asimplecustomizable Microprocessor.- Rapid Prototyping Using FPLDS - Vuman Case Study.- to VHDL.- Objects, Data Types and Processes.- VHDL and Logic Synthesis.- Example Designs and Problems.- to Verilog HDL.- Verilog and Logic Synthesis by Examples.- A Verilog Example: Pipelined Simp.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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