Digital Logic Design Using Verilog: Coding and RTL Synthesis

Author:   Vaibbhav Taraate
Publisher:   Springer, India, Private Ltd
Edition:   1st ed. 2016
ISBN:  

9788132227892


Pages:   416
Publication Date:   21 May 2016
Format:   Hardback
Availability:   Manufactured on demand   Availability explained
We will order this item for you from a manufactured on demand supplier.

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Digital Logic Design Using Verilog: Coding and RTL Synthesis


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Full Product Details

Author:   Vaibbhav Taraate
Publisher:   Springer, India, Private Ltd
Imprint:   Springer, India, Private Ltd
Edition:   1st ed. 2016
Weight:   8.602kg
ISBN:  

9788132227892


ISBN 10:   8132227891
Pages:   416
Publication Date:   21 May 2016
Audience:   College/higher education ,  Postgraduate, Research & Scholarly
Format:   Hardback
Publisher's Status:   Active
Availability:   Manufactured on demand   Availability explained
We will order this item for you from a manufactured on demand supplier.

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Reviews

“This book presents digital logic design using the hardware description language known as Verilog. … The book will help readers learn digital logic design and become familiar enough with it to work with it further in the future. It is mainly aimed as a textbook for undergraduate students to implement digital logic design in a lab. The book discusses logic design in a well-structured way covering basic to intermediate concepts.” (J. Arul, Computing Reviews, April, 2017)


This book presents digital logic design using the hardware description language known as Verilog. ... The book will help readers learn digital logic design and become familiar enough with it to work with it further in the future. It is mainly aimed as a textbook for undergraduate students to implement digital logic design in a lab. The book discusses logic design in a well-structured way covering basic to intermediate concepts. (J. Arul, Computing Reviews, April, 2017)


Author Information

Vaibbhav Taraate is Entrepreneur and Mentor at ""Semiconductor Training @ Rs.1"". He holds a BE (Electronics) degree from Shivaji University, Kohlapur in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his MTech (Aerospace Control and Guidance)  in 1999 from IIT Bombay. He has over 15 Years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.

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