Design of Interconnection Networks for Programmable Logic

Author:   Guy Lemieux ,  David Lewis
Publisher:   Springer-Verlag New York Inc.
Edition:   Softcover reprint of the original 1st ed. 2004
ISBN:  

9781441954152


Pages:   206
Publication Date:   21 September 2011
Format:   Paperback
Availability:   Out of stock   Availability explained
The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available.

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Design of Interconnection Networks for Programmable Logic


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Overview

This book presents the latest research results on the design of interconnect for programmable logic. The emphasis is on building the knowledge and tools for the automatic generation of interconnect structures. In this regard, the book presents design methodologies and applications for sparsely populated crossbars, clusters of lookup tables, switch blocks, and transistor-level routing switch design. It provides valuable information for both designers and architects about the area and delay implications of programmable interconnect. FPGA architects and System-on-Chip designers interested in exploring the integration of custom logic and programmable logic will find this work particularly useful.

Full Product Details

Author:   Guy Lemieux ,  David Lewis
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   Softcover reprint of the original 1st ed. 2004
Dimensions:   Width: 15.50cm , Height: 1.20cm , Length: 23.50cm
Weight:   0.361kg
ISBN:  

9781441954152


ISBN 10:   1441954155
Pages:   206
Publication Date:   21 September 2011
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Paperback
Publisher's Status:   Active
Availability:   Out of stock   Availability explained
The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available.

Table of Contents

1. Introduction.- 2. Interconnection Networks.- 3. Models, Methodology and CAD Tools.- 4. Sparse Crossbar Design.- 5. Sparse Cluster Design.- 6. Routing Switch Circuit Design.- 7. Switch Block Design.- 8. Conclusions.- Appendices.- A Switch Blocks: Reduced Flexibility.- A.1 Introduction.- A.4 Results.- A.5 Summary.- B Switch Blocks: Diverse Design Instances.- C VPRx: VPR Extensions.- C.1 Determination of Router Effort.- C.2 Routing Graph and Netlist Changes (Sparse Clusters).- C.3 Area and Delay Calculation Improvements.- C.4 Runtime Improvements.- C.5 Experimental Noise Reduction.- C.6 Correctness Changes.- References.

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