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OverviewThis book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable. Full Product DetailsAuthor: Brandon Noia , Krishnendu ChakrabartyPublisher: Springer International Publishing AG Imprint: Springer International Publishing AG Edition: 2014 ed. Dimensions: Width: 15.50cm , Height: 1.60cm , Length: 23.50cm Weight: 5.685kg ISBN: 9783319023779ISBN 10: 3319023772 Pages: 245 Publication Date: 02 December 2013 Audience: Professional and scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: Manufactured on demand  We will order this item for you from a manufactured on demand supplier. Table of ContentsIntroduction.- Wafer Stacking and 3D Memory Test.- Built-in Self-Test for TSVs.- Pre-Bond TSV Test Through TSV Probing.- Pre-Bond TSV Test Through TSV Probing.- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths.- Post-Bond Test Wrappers and Emerging Test Standards.- Test-Architecture Optimization and Test Scheduling.- Conclusions.ReviewsAuthor InformationKrishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM. Tab Content 6Author Website:Countries AvailableAll regions |
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