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OverviewThis reference offers practical and proven design-for-testability (DFT) solutions to chip and system design engineers, test engineers and product managers at the silicon level as well as at the board and systems levels. Designers will see how the implementation of embedded test enables simplification of silicon debug and system bring-up. Test engineers will determine how embedded test provides a superior level of at-speed test, diagnosis and measurement without exceeding the capabilities of their equipment. Product managers will learn how the time, resources and costs associated with test development, manufacture cost and lifecycle maintenance of their products can be significantly reduced by designing embedded test in the product. A complete design flow and analysis of the impact of embedded test on a design aims to help solve problems before any DFT is attempted. Full Product DetailsAuthor: Benoit Nadeau-DostiePublisher: Springer Imprint: Springer Edition: 2000 ed. Volume: 15 Dimensions: Width: 17.80cm , Height: 1.50cm , Length: 25.40cm Weight: 1.570kg ISBN: 9780792386698ISBN 10: 0792386698 Pages: 239 Publication Date: 30 September 1999 Audience: Professional and scholarly , General/trade , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsTechnology Overview.- Memory Test and Diagnosis.- Logic Test and Diagnosis.- Embedded Test Design Flow.- Hierarchical Core Test.- Test and Measurement for PLLs and ADCs.- System Test and Diagnosis.- System Reuse of Embedded Test.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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