Overview

This book provides a single-source reference on carbon nanotubes for interconnect applications. It presents the recent advances in modelling and challenges of carbon nanotube (CNT)-based VLSI interconnects. Starting with a background of carbon nanotubes and interconnects, this book details various aspects of CNT interconnect models, the design metrics of CNT interconnects, crosstalk analysis of recently proposed CNT interconnect structures, and geometries. Various topics covered include the use of semiconducting CNTs around metallic CNTs, CNT interconnects with air gaps, use of emerging ultra low-k materials and their integration with CNT interconnects, and geometry-based crosstalk reduction techniques. This book will be useful for researchers and design engineers working on carbon nanotubes for interconnects for both 2D and 3D integrated circuits.

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9789811588907

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Dr. P. Uma Sathyakam is working as an Assistant Professor in the School of Electrical Engineering, Vellore Institute of Technology, Vellore, India since December 2012. He received his B.Sc. Electronics degree from the University of Kerala, Thiruvananthapuram in 2007, the M.Sc. degree in Applied Electronics from Bharathiar University, Coimbatore, in 2009, M.S. (by Research) in Nanoelectronics from VIT University in 2011 and the Ph.D. degree in Nanoelectronics from Vellore Institute of Technology in 2018. He was a Research Fellow in an MHRD sponsored project on ‘online lab in microelectronics and VLSI’ from July 2009 to July 2010 in VIT and was a Research Associate from August 2010 to June 2011 during his M.S. in VIT. His areas of interest are nano-scale interconnects, carbon nanotube electronics, graphene and novel electronic materials, and futuristic electron devices.He published 18 journal and conference papers of international repute and a book on ‘VHDL Implementation of a 16-bit microprocessor’. He is a senior member of IEEE. Dr. Partha Sharathi Mallick is a Professor and former Dean of the School of Electrical Engineering, Vellore Institute of Technology, Vellore, India. He is also the Director of Office of the Ranking and Accreditation, VIT. He was the Technical Head of IAAB Electronics a Swedish Industry in Bangladesh. He led various research teams and developed online laboratory in microelectronics, Monte Carlo simulator of compound semiconductors, nanostructured MIM capacitor, and low-cost electric fencers. He has authored more than 100 research papers in different journals and conferences of international repute. He is the past Chapter Chair and a present Chapter Adviser of the IEEE-EDS VIT of Region 10 Asia-Pacific. He was an enlisted technical innovator of India in 2007. He has published a book on MATLAB and Simulink and in IET, UK, and has published his book chapter on MIM Capacitor in June 2016. His areas of interest are finding new materials and technology for future nano-scale electronics.

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