Overview

This title carefully details design tools and techniques for high-performance ASIC design. Using these techniques, the performance of ASIC designs can be improved by two to three times. Important topics include: improving performance through microarchitecture; timing-driven floorplanning; controlling and exploiting clock skew; high performance latch-based design in an ASIC methodology; automatically identifying and synthesizing complex logic gates; automated cell sizing to increase performance and reduce power; and controlling process variation. These techniques are illustrated by designs running two to three times the speed of typical ASICs in the same process generation.

Full Product Details

Author:   David Chinnery ,  Kurt Keutzer
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   2002 ed.
Dimensions:   Width: 15.50cm , Height: 2.30cm , Length: 23.50cm
Weight:   1.730kg
ISBN:  

9781402071133

ISBN 10:   1402071132
Pages:   414
Publication Date:   30 June 2002
Audience:   College/higher education ,  Professional and scholarly ,  Postgraduate, Research & Scholarly ,  Professional & Vocational
Format:   Hardback
Publisher's Status:   Active
Availability:   In Print  
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Table of Contents

and Overview of the Book.- Contributing Factors.- Improving Performance through Microarchitecture.- Reducing the Timing Overhead.- High-Speed Logic, Circuits, Libraries and Layout.- Finding Peak Performance in a Process.- Design Techniques.- Physical Prototyping Plans for High Performance.- Automatic Replacement of Flip-Flops by Latches in ASICs.- Useful-Skew Clock Synthesis Boosts ASIC Performance.- Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing.- Design Optimization with Automated Flex-Cell Creation.- Exploiting Structure and Managing Wires to Increase Density and Performance.- Semi-Custom Methods in a High-Performance Microprocessor Design.- Controlling Uncertainty in High Frequency Designs.- Increasing Circuit Performance through Statistical Design Techniques.- Design Examples.- Achieving 550MHz in a Standard Cell ASIC Methodology.- The iCORE™ 520MHz Synthesizable CPU Core.- Creating Synthesizable ARM Processors with Near Custom Performance.

Reviews

From the reviews: This book unveils the mystery behind the performance gap between ASIC and Custom design and shows how to close the gap with minimal design effort. A must read for every ASIC or ASSP designer. (William J. Dally, Professor, Stanford University) Most IP core providers must provide high-performance designs within the constraints of an ASIC methodology. I'm optimistic that careful application of the techniques in this book will enable me to design embedded processors that do indeed close 'the Gap Between ASIC and Custom'. (Kees Vissers, Director of Architecture, Trimedia Technologies Inc.) This book provides a comprehensive explanation of why ASICs fall so far behind custom ICs in performance, and then shows how better tools, libraries and methodologies can narrow the gap. It's a must read for ASIC designers who want to boost performance - or custom designers who want to speed time to market with ASIC-like design methodologies. (Richard Goering, EDA Editorial Director, EE Times) I've heard there is a price on the authors' heads. Power Users don't like people who give away their secrets. (Gary Smith, Chief Analyst, Dataquest) This book reflects the best research to date on understanding the tradeoffs between full-custom intellectual property blocks and synthesized intellectual-property blocks - a topic we could only touch on in the Reuse Methodology Manual. It is required reading for anyone engaged in system-on-a-chip design. (Michael Keating, author of the Reuse Methodology Manual, Vice-President, Synopsys) Solves one of life's little mysteries[...] It looks like it should become required reading for the IC innovators of this millennium. (Neil Weste, author of Principles of CMOS VLSI Design, Cisco Systems, Inc.)

From the reviews: <br> This book unveils the mystery behind the performance gap between ASIC and Custom design and shows how to close the gap with minimal design effort. A must read for every ASIC or ASSP designer. <br>(William J. Dally, Professor, Stanford University) <br> Most IP core providers must provide high-performance designs within the constraints of an ASIC methodology. I'm optimistic that careful application of the techniques in this book will enable me to design embedded processors that do indeed close the Gap Between ASIC and Custom'. <br>(Kees Vissers, Director of Architecture, Trimedia Technologies Inc.)<br> This book provides a comprehensive explanation of why ASICs fall so far behind custom ICs in performance, and then shows how better tools, libraries and methodologies can narrow the gap. It's a must read for ASIC designers who want to boost performance - or custom designers who want to speed time to market with ASIC-like design methodologies. <br>(Richard Goering, EDA Editorial Director, EE Times)<br> I've heard there is a price on the authors' heads. Power Users don't like people who give away their secrets. <br>(Gary Smith, Chief Analyst, Dataquest)<br> This book reflects the best research to date on understanding the tradeoffs between full-custom intellectual property blocks and synthesized intellectual-property blocks - a topic we could only touch on in the Reuse Methodology Manual. It is required reading for anyone engaged in system-on-a-chip design. <br>(Michael Keating, author of the Reuse Methodology Manual, Vice-President, Synopsys) <br> Solves one of life's little mysteries[...] It looks like it should become required reading for the IC innovators ofthis millennium. <br>(Neil Weste, author of Principles of CMOS VLSI Design, Cisco Systems, Inc.)

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