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OverviewRichard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. Full Product DetailsAuthor: Richard MundenPublisher: Elsevier Science & Technology Imprint: Elsevier Science & Technology ISBN: 9786611008284ISBN 10: 6611008284 Pages: 336 Publication Date: 01 January 2005 Audience: General/trade , General Format: Electronic book text Publisher's Status: Active Availability: Out of stock  The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available. Table of ContentsReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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