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OverviewA comprehensive guidebook, ARM Synthesizable Designs with Actel FPGAs features: Verilog HDL Synthesis and Simulation; Actel IGLOO for Low Power, Fusion for Mixed Signal, and ProASIC3 for Performance Applications; Flash Lock Technology for data secure designs and instant on Flash CMOS technology; ARM CortexM1 and ARM7S/MP7 enabled FPGA design with royalty-free IP; State of the art SoC EDA synthesis and simulation tools; Actel, Mentor Graphics, and Synopsys free one-year FPGA design tool licenses; Actel DVDROM: Libero FPGA design tools for ARM CortexM1 & ARM7TDMI; and, ARM DVDROM: ARM developers reference manuals and tools. Full Product DetailsAuthor: Peter Roy Ateshian , Daniel Pio ZulaicaPublisher: McGraw-Hill Education - Europe Imprint: McGraw-Hill Professional ISBN: 9780071622813ISBN 10: 0071622810 Pages: 600 Publication Date: 01 June 2010 Audience: Professional and scholarly , Professional & Vocational Format: Mixed media product Publisher's Status: Forthcoming Availability: In Print  Limited stock is available. It will be ordered for you and shipped pending supplier's limited stock. Table of ContentsModule-section 1: HDL ( Verilog hardware description language) Simulation and Synthesis and FPGA basic logic configuration. Ch 1 Review of Synthesizable Verilog HDL (hardware description language) Ch 2 Simulation, regression and Formal verification of Verilog HDL (hardware description language) digital designs. Ch 3 ModelSim, Precision and Synplify Pro Simulation and Synthesis EDA (Electronic Design Automation) tools for digital design. Ch 4 Actel FPGA architectures, benefits, granularity, logic gate mapping equivalency, I/O, clocking, PLL and DDR options. Ch 5 Actel Libero design flow introduction for Reconfigurable EE/Flash based PASIC3 and Fusion technology. Module 2 ARM*/Cortex ISA (instruction set architecture), IP (intellectual property) library and RTL structure. Ch 6 ARM* ISA (instruction set architecture) instruction pipelines Ch 7 ARM*/AMBA buss architecture describing registers, datapath, co-processor and SoC memory options Ch 8 ARM/AMBA peripherals and IP (intellectual property) library Ch 9 MP7-ARM7 SoC HDL (hardware description language) example built on the Actel Fusion device. Module 3: IP (intellectual property) library, Synthesizing, Place and Routing a peripheral, then hierarchically a SoC. Ch 10 FIFO and I/O HDL (hardware description language) to gates examples. Ch 11 DDR (double data rate) HDL (hardware description language) to gates example. Ch 12 MP7 SoC HDL (hardware description language) to gates example with 10 ARM7 peripherals. Complete a h/w architecture HDL (hardware description language) design cycle. Module 4: Programming the MP7/ARM7 with user applications. Ch 13. ARM-KEIL Real View and GNU tools environment for user software applications development. Assembly and C programming examples Ch 14 ARM7/MP7 SoC HVAC application examples. Complete a software design modification cycle. Module 5: Appendices Ch 15 A: Modelsim user manual Ch 16 B. Precision user manual Ch 17 C. Synplify Pro user manual Ch 18 D. Libero user manual Ch 19 E. Stanford University Raksha project using a modified SPARC Leon3 Verilog HDL and implemented on a Xilinx XUP Board. Ch 20 F. Fusion Development System with options Ch 21 G. Actel University Board user manualReviewsAuthor InformationPeter Ateshian lectures on VLSI Mixed-Signal, DSP, RF, Digital Logic Design, Error Control Coding, Satellite & Telecommunications, Modern Operating Systems, Nanotechnology, and Systems Engineering at the Naval Postgraduate School in Monterey, California. Daniel P. Zulaica has been contributing to research and laboratory education at the U.S. Naval Postgraduate School from 1987 to the present with the Department of Electrical and Computer Engineering. He has also contributed to articles in IEEE and other publications. Tab Content 6Author Website:Countries AvailableAll regions |
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