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OverviewThis book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required. Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures. Full Product DetailsAuthor: Husain Parvez , Habib MehrezPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: 2011 ed. Dimensions: Width: 15.50cm , Height: 0.90cm , Length: 23.50cm Weight: 0.454kg ISBN: 9781489987884ISBN 10: 1489987886 Pages: 150 Publication Date: 13 October 2014 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Manufactured on demand  We will order this item for you from a manufactured on demand supplier. Table of ContentsIntroduction.- State of the Art.- FPGA Layout Generation.- ASIF: Application Specific Inflexible FPGA.- ASIF using Heterogeneous Logic Blocks.- ASIF Hardware Generation.- Conclusion and Future Lines of Research.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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