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OverviewFull Product DetailsAuthor: Woorham Bae (Senior SerDes Engineer, Ayar Labs, Santa Clara, USA) , Deog-Kyoon Jeong (Professor, Seoul National University, South Korea)Publisher: Institution of Engineering and Technology Imprint: Institution of Engineering and Technology Dimensions: Width: 15.60cm , Height: 1.80cm , Length: 23.40cm Weight: 0.567kg ISBN: 9781785618017ISBN 10: 1785618016 Pages: 256 Publication Date: 19 August 2020 Audience: College/higher education , Professional and scholarly , Tertiary & Higher Education , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsChapter 1: Introduction Chapter 2: Introduction to phase noise and jitter Chapter 3: CMOS oscillators Chapter 4: Phase noise theory for CMOS oscillators Chapter 5: Introduction to PLL/DLL Chapter 6: PLL loop dynamics and jitter Chapter 7: DLL loop dynamics and jitter Chapter 8: Phase noise suppression techniques 1: subsampling PLL Chapter 9: Phase noise suppression techniques 2: all-digital PLL Chapter 10: Phase noise suppression techniques 3: injection locking Chapter 11: Phase noise suppression techniques 4: clock multiplying DLL Appendix A: Figure of merits (FoMs) for evaluating VCOs and PLLs Appendix B: Survey on state-of-the-art clock generators Appendix C: System Verilog modeling of CMOS clock generator including jitter Appendix D: Noise sources in MOSFET transistorReviewsAuthor InformationWoorham Bae received the B.S. and Ph.D. degrees in Electrical and Computer Engineering from Seoul National University, Seoul, Korea, in 2010 and 2016, respectively. In 2016, he was with the Inter-University Semiconductor Research Center, Seoul National University, Seoul, Korea. From 2017 to 2019, he was with the University of California, Berkeley, CA, as a Postdoctoral Researcher. He is currently a Senior SerDes Engineer with Ayar Labs, Santa Clara, CA. His current research interests include integrated circuits for silicon photonics, high-speed I/O circuits and architectures, nonvolatile memory systems, and agile hardware design methodology. Dr. Bae received the IEEE Circuits and Systems Society Outstanding Young Author Award in 2018, the Distinguished Ph.D. Dissertation Award from the Department of Electrical and Computer Engineering, Seoul National University in 2016, the IEEE Circuits and Systems Society Pre-Doctoral Scholarship in 2016, and the IEEE Solid-State Circuits Society STG Award in 2015. Deog-Kyoon Jeong received the B.S. and M.S. degrees in Electronics Engineering from Seoul National University, Seoul, South Korea, in 1981 and 1984, respectively, and the Ph.D. degree in Electrical Engineering and Computer Sciences from the University of California at Berkeley, Berkeley, CA, USA, in 1989. From 1989 to 1991, he was a member of the Technical Staff with Texas Instruments, Dallas, TX, USA. He worked on the modeling and design of BiCMOS gates and the single-chip implementation of the SPARC architecture. Then, he joined the faculty of the Department of Electronics Engineering and Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea, where he is currently an Endowed-Chair Professor. He was one of cofounders of Silicon Image, Sunnyvale, CA, now Lattice Semiconductor, which specialized in digital interface circuits for video displays such as DVI and HDMI. His main research interests include the design of high-speed I/O circuits, phase-locked loops, and memory system architecture. Dr. Jeong was a recipient of the ISSCC Takuo Sugano Award in 2005 for Outstanding Far-East Paper. He is a Fellow of the IEEE. Tab Content 6Author Website:Countries AvailableAll regions |
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