Overview

This monograph addresses the problem of device layout for high-performance custom analog cells. In particular, an alternative placement and routing formulation is proposed that is designed to minimize the cost in layout quality that is traditionally associated with analog layout automation. The goal of analog layout is to minimize the effects of layout induced performance degradation while, at the same time, maximizing the area utilization of the circuit. Human layout experts observe a variety of analog-specific layout constraints and exploit a range of geometric optimizations to achieve these performance and density goals. This work is directed at discovering how these constraints and optimizations can best be incorporated into automatic layout optimization. Two of the products of this research are a analog device-level placer, KOAN, and a analogue device-level router, ANAGRAM II [40], which incorporate a more comprehensive set of layout constraints and geometric optimizations than in any previous systems. The work focuses on the formulation, algorithms, and certain relevant implementation details of KOAN and ANAGRAM II.

Full Product Details

Author:   John M. Cohn ,  David J. Garrod ,  Rob A. Rutenbar ,  Rick Carley
Publisher:   Springer
Imprint:   Springer
Edition:   1994 ed.
Volume:   263
Dimensions:   Width: 15.50cm , Height: 1.90cm , Length: 23.50cm
Weight:   1.350kg
ISBN:  

9780792394310

ISBN 10:   0792394313
Pages:   285
Publication Date:   31 January 1994
Audience:   College/higher education ,  Professional and scholarly ,  Undergraduate ,  Postgraduate, Research & Scholarly
Format:   Hardback
Publisher's Status:   Active
Availability:   In Print  
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Table of Contents

1 Introduction.- 1.1 Focus.- 1.2 Introduction.- 1.3 Analog Cell Layout: Important Concerns.- 1.4 Semi-Custom Analog Layout Technologies.- 1.5 Layout Strategy.- 1.6 Overview.- 2 Basic Placement.- 2.1 Introduction.- 2.2 Simulated Annealing for Device-Level Placement.- 2.3 Basic Placement Formulation.- 2.4 KOAN Basic Placement Functionality.- 2.5 KOAN Basic Placement Results.- 2.6 Summary.- 3 Topological Placement.- 3.1 Introduction.- 3.2 Modeling Topological Constraints.- 3.3 Placement for Device Matching.- 3.4 Placement for Layout Symmetry.- 3.5 Placement for System-Level Topological Constraints.- 3.6 General Implementation Issues.- 3.7 Topologically-Constrained Results.- 3.8 Summary.- 4 Geometry Sharing Placement.- 4.1 Introduction.- 4.2 Geometry Sharing Optimizations in Analog VLSI Layout.- 4.3 Supporting Geometry Sharing Optimizations.- 4.4 Geometry Sharing Results.- 4.5 Placement Optimization Dynamics.- 4.6 Summary.- 5 Line-Expansion Routing.- 5.1 Line-Expansion Routing.- 5.2 Basic Path Finding.- 5.3 Other Basic Routing Issues.- 5.4 Results.- 5.5 Summary.- 6 Integrated Rerouting.- 6.1 Need for Ripup.- 6.2 Rip-up Methodologies.- 6.3 Integrated Rip-up in ANAGRAM II.- 6.4 Embedding: Controlling Rip-up/Reroute.- 6.5 Summary.- 7 Symmetric Routing.- 7.1 Thermal Matching.- 7.2 Parametric Device Matching.- 7.3 Symmetric Placement.- 7.4 Symmetric Routing: Motivations.- 7.5 Symmetric Routing in ANAGRAM II.- 7.6 Routability Issues in Symmetric Routing.- 7.7 Results.- 7.8 Summary.- 8 Crosstalk Avoidance Routing.- 8.1 Crosstalk Avoidance Routing: Background.- 8.2 Crosstalk Avoidance in ANAGRAM II.- 8.3 Path Finding and Crosstalk Penalties.- 8.4 Results.- 8.5 Summary.- 9 Additional KOAN/ANAGRAM II Results.- 9.1 Introduction.- 9.2 System-Level Overview.- 9.3 Scaling behavior.- 9.4Additional Comparisons with Manual Layout.- 9.5 Technology Remapping.- 9.6 Fabrication Example.- 9.7 Incremental re-spacing.- 9.8 Summary.- 10 Conclusions and Future Work.

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