Overview

This textbook is intended to serve as a practical guide for the design of complex digital logic circuits such as digital control circuits, network interface circuits, pipelined arithmetic units, and RISC microprocessors. It is an advanced digital logic design textbook that emphasizes the use of synthesizable VHDL code and provides numerous fully worked-out practical design examples including a Universal Serial Bus interface, a pipelined multiply-accumulate unit, and a pipelined microprocessor for the ARM THUMB architecture.

Full Product Details

Author:   Sunggu Lee (Pohang University of Science and Technology)
Publisher:   Cengage Learning, Inc
Imprint:   CL Engineering
Edition:   New edition
Dimensions:   Width: 19.20cm , Height: 2.50cm , Length: 24.00cm
Weight:   0.940kg
ISBN:  

9780534466022

ISBN 10:   0534466028
Pages:   488
Publication Date:   25 April 2005
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Hardback
Publisher's Status:   Out of Print
Availability:   Awaiting stock  

Table of Contents

Preface Chapter 1 Condensed Overview of Introductory Digital Logic Design 1.1Number Formats 1.2Combinational Logic 1.2.1Combinational Logic Devices 1.2.2Combinational Logic Circuit Design 1.3Sequential Logic 1.3.1Sequential Logic Devices 1.3.2Synchronous Sequential Circuit Design 1.3.3Hazards and Glitches 1.3.4Mestastability Chapter 2Digital Logic Design Using Hardware Description Languages 2.1Hardware description Languages 2.2Design Flow 2.3Synthesis 2.4Register Transfer Level Notation 2.5Logic Simulation 2.6Properties of Actual Circuits Chapter 3Introduction to VHDL and Test Benches 3.1Overview 3.2VHDL Basics 3.2.1Entity and Architecture 3.2.2Signals, Data, Types, Constants and Operators 3.2.3Libraries and Packages 3.2.4Structural and Behavioral 3.3Testing and the Test Bench 3.3.1Manufacturing Testing 3.3.2Functional Testing 3.3.3Test Benches 3.3.4VHDL Test Bench 3.4More Advanced VHDL Concepts 3.4.1Concurrent and Sequential VHDL 3.4.2Variables and Signals 3.4.3Delay Modeling 3.4.4Attributes 3.4.5Procedures and Functions 3.4.6Generics and Modeling a Bidirectional Bus 3.5Construction of Complete VHDL Programs 3.5.1Combinational Logic Circuits 3.5.2Sequential Logic Circuits 3.5.3Behavioral Modeling of More Complex Circuits Chapter 4High-Level VHDL Coding for Synthesis 4.1Register Transfer Level Notation 4.2Combinational Logic Synthesis 4.2.1Using Concurrent Signal Assignment Statements for Combinational Logic 4.2.2Using Process Blocks for Combinational Logic 4.2.3Complex Combinational Logic Example 4.3Sequential Logic Synthesis 4.4Synthesis Heuristics 4.5Synthesis Using a Commercial Tool 4.6High-Level VHDL Coding Chapter 5State Machine Design 5.1Manual State Machine Design 5.1.1Pseudocode 5.1.2RTL Program 5.1.3Datapath 5.1.4State Diagram 5.1.5Control Logic 5.1.6State Machine Design Using ASM Charts 5.2Automatic Synthesis-Based State Machine Design 5.2.1Automatic Synthesis-Based Design Procedure 5.2.2Algorithm to HDL Code Conversion 5.3Design Example: Vending Machine 5.3.1Automatic State Machine Design for a Vending Machine 5.3.2Manual State Machine Design for a Vending Machine 5.3.3Timing Diagram 5.3.4Correspondence Between Automatic and Manual Designs 5.4Design Example: LCD Controller 5.4.1Target LCD Module 5.4.2VHDL Solution Chapter 6FPGA and Other Programmable Logic Devices 6.1Programmable Logic Devices 6.1.1Circuit Customization 6.1.2Programmable Logic Arrays 6.1.3Programmable Read Only Memories 6.1.4Programmable AND-Array Logic 6.2Field Programmable Gate Arrays 6.2.1Gate Arrays 6.2.2FPGA Overview 6.2.3Xilinx FPGA Example 6.2.4FPGA Configuration 6.2.5Xilinx Spartan-II FPGA Configuration Example 6.2.6Boundary Scan Chapter 7Design of a USB Protocol Analyzer 7.1Overview of USB Full-Speed Mode 7.1.1Packet Transfer Protocol 7.1.2Initialization Sequence 7.1.3Physical Layer Interface 7.1.4USB Packets 7.1.5Cyclic Redundancy Checks 7.1.6Observation of Actual USB Signals 7.2Design Overview 7.2.1State Machine 7.2.2Subcircuit Partitioning 7.3VHDL Solution 7.3.1Digital Phase Locked Loop 7.3.2NRZI-to-Binary Converter 7.3.3CRC Checker Subcircuits 7.3.4Packet ID Recognizer 7.3.5State Machine Subcircuit 7.3.6Top-Level Circuit 7.3.7Test Bench Code for Entire Circuit 7.4Simulation Results Chapter 8Design of Fast Arithmetic Units 8.1Adder Designs 8.1.1Ripple Carry adder 8.1.2Carry Lookahead Adder 8.1.3Carry Save Adder 8.2Multiplier Designs 8.2.1Combinational Multiplier 8.2.2Sequential Multiplier 8.2.3Fast Multiplication 8.2.4Multiply-Accumulate Units 8.3Pipelined Functional Units 8.3.1Introduction to Pipelining 8.3.2Pipelined Multiply-Accumulate Units 8.4HDL Implementations 8.4.1HDL Implementation Overview 8.4.2HDL Design for a Pipelined Multiply-Accumulate Unit 8.4.3Test Bench and Simulation Results Chapter 9Design of a Pipelined RISC Microprocessor 9.1Introduction to Microprocessors 9.1.1Reduced Instruction Set Computers 9.1.2Basic Computer Operation 9.2The THUMB Microprocessor Architecture 9.2.1Thumb Programming Model 9.2.2Overview of the THUMB Instruction Set 9.3Instruction Pipeline Design 9.3.1Pipeline Hazards 9.3.2Hazard Prevention Techniques 9.3.3Pipeline Hazard Solutions Adopted 9.4HDL Implementation of the THUMB Pipeline 9.4.1VHDL THUMB Implementation 9.4.2Test Bench Based Verification ATHUMB Instruction Set Listing

Reviews

Preface Chapter 1 Condensed Overview of Introductory Digital Logic Design 1.1 Number Formats 1.2 Combinational Logic 1.2.1 Combinational Logic Devices 1.2.2 Combinational Logic Circuit Design 1.3 Sequential Logic 1.3.1 Sequential Logic Devices 1.3.2 Synchronous Sequential Circuit Design 1.3.3 Hazards and Glitches 1.3.4 Mestastability Chapter 2 Digital Logic Design Using Hardware Description Languages 2.1 Hardware description Languages 2.2 Design Flow 2.3 Synthesis 2.4 Register Transfer Level Notation 2.5 Logic Simulation 2.6 Properties of Actual Circuits Chapter 3 Introduction to VHDL and Test Benches 3.1 Overview 3.2 VHDL Basics 3.2.1 Entity and Architecture 3.2.2 Signals, Data, Types, Constants and Operators 3.2.3 Libraries and Packages 3.2.4 Structural and Behavioral 3.3 Testing and the Test Bench 3.3.1 Manufacturing Testing 3.3.2 Functional Testing 3.3.3 Test Benches 3.3.4 VHDL Test Bench 3.4 More Advanced VHDL Concepts 3.4.1 Concurrent and Sequential VHDL 3.4.2 Variables and Signals 3.4.3 Delay Modeling 3.4.4 Attributes 3.4.5 Procedures and Functions 3.4.6 Generics and Modeling a Bidirectional Bus 3.5 Construction of Complete VHDL Programs 3.5.1 Combinational Logic Circuits 3.5.2 Sequential Logic Circuits 3.5.3 Behavioral Modeling of More Complex Circuits Chapter 4 High-Level VHDL Coding for Synthesis 4.1 Register Transfer Level Notation 4.2 Combinational Logic Synthesis 4.2.1 Using Concurrent Signal Assignment Statements for Combinational Logic 4.2.2 Using Process Blocks for Combinational Logic 4.2.3 Complex Combinational Logic Example 4.3 Sequential Logic Synthesis 4.4 Synthesis Heuristics 4.5 Synthesis Using a Commercial Tool 4.6 High-Level VHDL Coding Chapter 5 State Machine Design 5.1 Manual State Machine Design 5.1.1 Pseudocode 5.1.2 RTL Program 5.1.3 Datapath 5.1.4 State Diagram 5.1.5 Control Logic 5.1.6 State Machine Design Using ASM Charts 5.2 Automatic Synthesis-Based State Machine Design 5.2.1 Automatic Synthesis-Based Design Procedure 5.2.2 Algorithm to HDL Code Conversion 5.3 Design Example: Vending Machine 5.3.1 Automatic State Machine Design for a Vending Machine 5.3.2 Manual State Machine Design for a Vending Machine 5.3.3 Timing Diagram 5.3.4 Correspondence Between Automatic and Manual Designs 5.4 Design Example: LCD Controller 5.4.1 Target LCD Module 5.4.2 VHDL Solution Chapter 6 FPGA and Other Programmable Logic Devices 6.1 Programmable Logic Devices 6.1.1 Circuit Customization 6.1.2 Programmable Logic Arrays 6.1.3 Programmable Read Only Memories 6.1.4 Programmable AND-Array Logic 6.2 Field Programmable Gate Arrays 6.2.1 Gate Arrays 6.2.2 FPGA Overview 6.2.3 Xilinx FPGA Example 6.2.4 FPGA Configuration 6.2.5 Xilinx Spartan-II FPGA Configuration Example 6.2.6 Boundary Scan Chapter 7 Design of a USB Protocol Analyzer 7.1 Overview of USB Full-Speed Mode 7.1.1 Packet Transfer Protocol 7.1.2 Initialization Sequence 7.1.3 Physical Layer Interface 7.1.4 USB Packets 7.1.5 Cyclic Redundancy Checks 7.1.6 Observation of Actual USB Signals 7.2 Design Overview 7.2.1 State Machine 7.2.2 Subcircuit Partitioning 7.3 VHDL Solution 7.3.1 Digital Phase Locked Loop 7.3.2 NRZI-to-Binary Converter 7.3.3 CRC Checker Subcircuits 7.3.4 Packet ID Recognizer 7.3.5 State Machine Subcircuit 7.3.6 Top-Level Circuit 7.3.7 Test Bench Code for Entire Circuit 7.4 Simulation Results Chapter 8 Design of Fast Arithmetic Units 8.1 Adder Designs 8.1.1 Ripple Carry adder 8.1.2 Carry Lookahead Adder 8.1.3 Carry Save Adder 8.2 Multiplier Designs 8.2.1 Combinational Multiplier 8.2.2 Sequential Multiplier 8.2.3 Fast Multiplication 8.2.4 Multiply-Accumulate Units 8.3 Pipelined Functional Units 8.3.1 Introduction to Pipelining 8.3.2 Pipelined Multiply-Accumulate Units 8.4 HDL Implementations 8.4.1 HDL Implementation Overview 8.4.2 HDL Design for a Pipelined Multiply-Accumulate Unit 8.4.3 Test Bench and Simulation Results Chapter 9 Design of a Pipelined RISC Microprocessor 9.1 Introduction to Microprocessors 9.1.1 Reduced Instruction Set Computers 9.1.2 Basic Computer Operation 9.2 The THUMB Microprocessor Architecture 9.2.1 Thumb Programming Model 9.2.2 Overview of the THUMB Instruction Set 9.3 Instruction Pipeline Design 9.3.1 Pipeline Hazards 9.3.2 Hazard Prevention Techniques 9.3.3 Pipeline Hazard Solutions Adopted 9.4 HDL Implementation of the THUMB Pipeline 9.4.1 VHDL THUMB Implementation 9.4.2 Test Bench Based Verification A THUMB Instruction Set Listing

Author Information

Sunggu Lee received the B.S.E.E. degree with highest distinction from the University of Kansas, Lawrence, in 1985 and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1987 and 1990, respectively. He is currently an Associate Professor in the Department of Electronic and Electrical Engineering at the Pohang University of Science and Technology (POSTECH), Pohang, Korea. Prior to this appointment, he was an Assistant Professor in the Department of Electrical Engineering at the University of Delaware in Newark, Delaware, U.S.A. From June 1997 to June 1998, he spent one year as a Visiting Scientist at the IBM T. J. Watson Research Center. His research interests are in parallel computing using clusters, fault-tolerant computing, and real-time computing.

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