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OverviewLarge system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing. Full Product DetailsAuthor: Mukund Sivaraman , Andrzej J. StrojwasPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: Softcover reprint of the original 1st ed. 1998 Dimensions: Width: 15.50cm , Height: 0.90cm , Length: 23.50cm Weight: 0.278kg ISBN: 9781461346395ISBN 10: 1461346398 Pages: 155 Publication Date: 13 September 2012 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Manufactured on demand  We will order this item for you from a manufactured on demand supplier. Table of Contents1 Introduction.- 2 Backgound.- 2.1 Timing Verification.- 2.2 Delay Fault Testing - Concepts And Terminology.- 3 Primitive Path Delay Fault Identification.- 3.1 Primitive Path Delay Fault Characteristics.- 3.2 Signal Stabilization Time Analysis - SSTA.- 3.3 Results and Observations.- 3.4 Synopsis.- 4 Timing Analysis.- 4.1 Primitive PDFs in the Context of Timing Analysis.- 4.2 Primitive PDF Identification Based Timing Analysis.- 4.3 Comparisons.- 4.4 Applicability.- 4.5 Results.- 4.6 Synopsis.- 5 Delay Fault Diagnosis.- 5.1 Background.- 5.2 A Framework for Diagnosis.- 5.3 A Diagnosability Metric.- Delay Fault Coverage.- 6.1 Previous Work.- 6.2 The New Coverage Metric.- 6.3 Distributed Path Delay Fault Coverage.- 6.4 Synopsis.- 7 Epilogue.- 7.1 Extensions.- References.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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